5M80ZE64I5N Datasheet, PDF (155/166 Pages) Altera Corporation – MAX V Device Handbook

Chapter 8: JTAG Boundary-Scan Testing in MAX V Devices
8–7
IEEE Std. 1149.1 BST Operation Control
When the TAP controller is in the TEST_LOGIC/RESET state, the BST circuitry is
disabled, the device is in normal operation, and the instruction register is initialized
with IDCODE as the initial instruction. During device power up, the TAP controller
starts in this TEST_LOGIC/RESET state. In addition, the TAP controller may be forced to
the TEST_LOGIC/RESET state by holding TMS high for five TCK clock cycles. After the
TEST_LOGIC/RESET state, the TAP controller remains in this state as long as TMS
continues to be held high while TCK is clocked.
Figure 8–6 shows the timing requirements for the IEEE Std. 1149.1 signals.
Figure 8–6. IEEE Std. 1149.1 Timing Waveforms (Note 1)
TMS
TDI
TCK
t_JCP
t_JCH
t_JCL
t_JPSU
t_JPH
TDO
Signal
to Be
Captured
Signal
to Be
Driven
t_JPZX
t_JSSU
t_JPCO
t_JSH
t_JSZX
t_JSCO
t_JPXZ
t_JSXZ
Note to Figure 8–6:
(1) For timing parameter values, refer to the DC and Switching Characteristics for MAX V Devices chapter.
To start the IEEE Std. 1149.1 operation, select an instruction mode by advancing the
TAP controller to the shift instruction register (SHIFT_IR) state and shift in the
appropriate instruction code on the TDI pin.
Figure 8–7 shows the entry of the instruction code into the instruction register. From
the RESET state, TMS is clocked with the pattern 01100 to advance the TAP controller to
SHIFT_IR state.
Figure 8–7. Selecting the Instruction Mode
TCK
TMS
TDI
TDO
TAP_ST ATE
SHIFT_IR
RUN_TEST/IDLE SELECT_IR_SCAN
SELECT_DR_SCAN
TEST_LOGIC/RESET
CAPTURE_IR
EXIT1_IR
December 2010 Altera Corporation
MAX V Device Handbook