5M80ZE64I5N Datasheet, PDF (118/166 Pages) Altera Corporation – MAX V Device Handbook

7–14
Chapter 7: User Flash Memory in MAX V Devices
Software Support for UFM Block
■ Data transfer can be initiated only when the bus is free.
■ The data on the SDA line must be stable during the high period of the clock. The
high or low state of the data line can only change when the clock signal on the SCL
line is low.
■ Any transition on the SDA line while the SCL is high indicates a start or stop
condition.
Table 7–5 lists the ALTUFM_I2C megafunction input and output interface signals.
Table 7–5. ALTUFM_I2C Interface Signals
Pin
SDA
Description
Serial Data/Address Line
SCL
Serial Clock Line
WP
Write Protect
A₂, A₁, A₀ Slave Address Input
Function
The bidirectional SDA port is used to transmit and receive serial data from the
UFM. The output stage of the SDA port is configured as an open drain pin to
perform the wired-AND function.
The bidirectional SCL port is used to synchronize the serial data transfer to and
from the UFM. The output stage of the SCL port is configured as an open drain
pin to perform a wired-AND function.
Optional active high signal that disables the erase and write function for
read/write mode. The ALTUFM_I2C megafunction gives you an option to
protect the entire UFM memory or only the upper half of memory.
These inputs set the UFM slave address. The A₆, A₅, A₄, A₃ slave address bits
are programmable, set internally to 1010 by default.
START and STOP Condition
The master always generates start (S) and stop (P) conditions. After the start
condition, the bus is considered busy. Only a stop (P) condition frees the bus. The bus
stays busy if the repeated start (Sr) condition is executed instead of a stop condition.
In this occurrence, the start (S) and repeated start (Sr) conditions are functionally
identical.
A high-to-low transition on the SDA line while the SCL is high indicates a start
condition. A low-to-high transition on the SDA line while the SCL is high indicates a
stop condition. Figure 7–9 shows the start and stop conditions.
Figure 7–9. Start and Stop Conditions
SDA
SDA
SCL
S
Start Condition
SCL
P
Stop Condition
MAX V Device Handbook
January 2011 Altera Corporation