5M80ZE64I5N Datasheet, PDF (35/166 Pages) Altera Corporation – MAX V Device Handbook

Chapter 2: MAX V Architecture
2–23
User Flash Memory Block
Program, Erase, and Busy Signals
The UFM block’s dedicated circuitry automatically generates the necessary internal
program and erase algorithm after the PROGRAM or ERASE input signals have been
asserted. The PROGRAM or ERASE signal must be asserted until the busy signal deasserts,
indicating the UFM internal program or erase operation has completed. The UFM
block also supports JTAG as the interface for programming and reading.
f For more information about programming and erasing the UFM block, refer to the
User Flash Memory in MAX V Devices chapter.
Auto-Increment Addressing
The UFM block supports standard read or stream read operations. The stream read is
supported with an auto-increment address feature. Deasserting the ARSHIFT signal
while clocking the ARCLK signal increments the address register value to read
consecutive locations from the UFM array.
Serial Interface
The UFM block supports a serial interface with serial address and data signals. The
internal shift registers within the UFM block for address and data are 9 bits and 16 bits
wide, respectively. The Quartus II software automatically generates interface logic in
LEs for a parallel address and data interface to the UFM block. Other standard
protocol interfaces such as SPI are also automatically generated in LE logic by the
Quartus II software.
f For more information about the UFM interface signals and the Quartus II LE-based
alternate interfaces, refer to the User Flash Memory in MAX V Devices chapter.
December 2010 Altera Corporation
MAX V Device Handbook