EPM7192SQC160-15 Datasheet, PDF(60/66 Page) Altera Corporation – High-performance, EEPROM-based programmable logic devices PLDs) based on second-generation MAX architecture

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EPM7192SQC160-15 Datasheet, PDF (60/66 Pages) Altera Corporation – High-performance, EEPROM-based programmable logic devices PLDs) based on second-generation MAX architecture

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MAX 7000 Programmable Logic Device Family Data Sheet

Figure 17. 68-Pin Package Pin-Out Diagram

Package outlines not drawn to scale.

I/O 10

VCCIO 11

(2) I/O/(TDI) 12

I/O 13

I/O 14

I/O 15

GND 16

I/O 17

I/O 18

(2) I/O/(TMS) 19

I/O 20

VCCIO 21

I/O 22

I/O 23

I/O 24

I/O 25

GND 26

EPM7064

EPM7096

60 I/O

59 I/O

58 GND

57 I/O/(TDO) (2)

56 I/O

55 I/O

54 I/O

53 VCCIO

52 I/O

51 I/O

50 I/O/(TCK) (2)

49 I/O

48 GND

47 I/O

46 I/O

45 I/O

44 I/O

68-Pin PLCC

Notes:

(1) The pin functions shown in parenthesis are only available in MAX 7000E and MAX

7000S devices.

(2) JTAG ports are available in MAX 7000S devices only.

Altera Corporation

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