EPM7192SQC160-15 Datasheet, PDF (40/66 Pages) Altera Corporation – High-performance, EEPROM-based programmable logic devices PLDs) based on second-generation MAX architecture

MAX 7000 Programmable Logic Device Family Data Sheet
Table 27. EPM7032S External Timing Parameters (Part 2 of 2) Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-5
-6
-7
-10
Min Max Min Max Min Max Min Max
f_ACNT
f_MAX
Maximum internal array clock (4)
frequency
Maximum clock frequency
(5)
175.4
250.0
142.9
200.0
116.3
166.7
100.0
125.0
MHz
MHz
Table 28. EPM7032S Internal Timing Parameters Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-5
-6
-7
-10
Min Max Min Max Min Max Min Max
t_IN
t_IO
t_FIN
t_SEXP
t_PEXP
t_LAD
t_LAC
t_IOE
t_OD1
t_OD2
t_OD3
t_ZX1
t_ZX2
t_ZX3
t_XZ
t_SU
t_H
t_FSU
t_FH
t_RD
t_COMB
t_IC
t_EN
t_GLOB
t_PRE
t_CLR
Input pad and buffer delay
I/O input pad and buffer delay
Fast input delay
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
Output buffer and pad delay C1 = 35 pF
Output buffer and pad delay C1 = 35 pF (6)
Output buffer and pad delay C1 = 35 pF
Output buffer enable delay C1 = 35 pF
Output buffer enable delay C1 = 35 pF (6)
Output buffer enable delay C1 = 35 pF
Output buffer disable delay C1 = 5 pF
Register setup time
0.8
Register hold time
1.7
Register setup time of fast
1.9
input
Register hold time of fast
0.6
input
Register delay
Combinatorial delay
Array clock delay
Register enable time
Global control delay
Register preset time
Register clear time
0.2
0.2
0.3
0.5 ns
0.2
0.2
0.3
0.5 ns
2.2
2.1
2.5
1.0 ns
3.1
3.8
4.6
5.0 ns
0.9
1.1
1.4
0.8 ns
2.6
3.3
4.0
5.0 ns
2.5
3.3
4.0
5.0 ns
0.7
0.8
1.0
2.0 ns
0.2
0.3
0.4
1.5 ns
0.7
0.8
0.9
2.0 ns
5.2
5.3
5.4
5.5 ns
4.0
4.0
4.0
5.0 ns
4.5
4.5
4.5
5.5 ns
9.0
9.0
9.0
9.0 ns
4.0
4.0
4.0
5.0 ns
1.0
1.3
2.0
ns
2.0
2.5
3.0
ns
1.8
1.7
3.0
ns
0.7
0.8
0.5
ns
1.2
1.6
1.9
2.0 ns
0.9
1.1
1.4
2.0 ns
2.7
3.4
4.2
5.0 ns
2.6
3.3
4.0
5.0 ns
1.6
1.4
1.7
1.0 ns
2.0
2.4
3.0
3.0 ns
2.0
2.4
3.0
3.0 ns
40
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