EPM7192SQC160-15 Datasheet, PDF (10/66 Pages) Altera Corporation – High-performance, EEPROM-based programmable logic devices PLDs) based on second-generation MAX architecture

MAX 7000 Programmable Logic Device Family Data Sheet
Figure 4 shows a MAX 7000E and MAX 7000S device macrocell.
Figure 4. MAX 7000E & MAX 7000S Device Macrocell
Logic Array
Parallel Logic
Expanders
(from other
macrocells)
Global Global
Clear Clocks
2
Product-
Term
Select
Matrix
Clock/
Enable
Select
VCC
Clear
Select
Fast Input Programmable
Select Register
Register
Bypass
PRN
D/T Q
ENA
CLRN
from
I/O pin
to I/O
Control
Block
36 Signals
from PIA
16 Expander
Product Terms
Shared Logic
Expanders
to PIA
Combinatorial logic is implemented in the logic array, which provides
five product terms per macrocell. The product-term select matrix allocates
these product terms for use as either primary logic inputs (to the OR and
XOR gates) to implement combinatorial functions, or as secondary inputs
to the macrocell’s register clear, preset, clock, and clock enable control
functions. Two kinds of expander product terms (“expanders”) are
available to supplement macrocell logic resources:
■ Shareable expanders, which are inverted product terms that are fed
back into the logic array
■ Parallel expanders, which are product terms borrowed from adjacent
macrocells
The Altera development system automatically optimizes product-term
allocation according to the logic requirements of the design.
For registered functions, each macrocell flipflop can be individually
programmed to implement D, T, JK, or SR operation with programmable
clock control. The flipflop can be bypassed for combinatorial operation.
During design entry, the designer specifies the desired flipflop type; the
Altera development software then selects the most efficient flipflop
operation for each registered function to optimize resource utilization.
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Altera Corporation