EPM7192SQC160-15 Datasheet, PDF (59/66 Pages) Altera Corporation – High-performance, EEPROM-based programmable logic devices PLDs) based on second-generation MAX architecture

MAX 7000 Programmable Logic Device Family Data Sheet
Figures 16 through 22 show the package pin-out diagrams for MAX 7000
devices.
Figure 16. 44-Pin Package Pin-Out Diagram
Package outlines not drawn to scale.
Pin 1
(2) I/O/(TDI)
I/O
I/O
GND
I/O
I/O
(2) I/O/(TMS)
I/O
VCC
I/O
I/O
Pin 12
Pin 34
EPM7032
44-Pin PQFP
I/O
I/O/(TDO) (2)
I/O
I/O
VCC
I/O
I/O
I/O/(TCK) (2)
I/O
GND
I/O
Pin 23
6 5 4 3 2 1 44 43 42 41 40
(2) I/O /(TDI) 7
I/O 8
I/O 9
GND 10
I/O 11
I/O 12
(2) I/O/(TMS) 13
I/O 14
VCC 15
I/O 16
I/O 17
EPM7032
EPM7032S
EPM7064
EPM7064S
39 I/O
38 I/O/(TDO) (2)
37 I/O
36 I/O
35 VCC
34 I/O
33 I/O
32 I/O/(TCK) (2)
31 I/O
30 GND
29 I/O
18 19 20 21 22 23 24 25 26 27 28
44-Pin PLCC
Pin 1
Pin 34
(2) I/O /(TDI)
I/O
I/O
GND
I/O
I/O
(2) I/O /(TMS)
I/O
VCC
I/O
I/O
EPM7032
EPM7032S
EPM7064
EPM7064S
I/O
I/O/(TDO) (2)
I/O
I/O
VCC
I/O
I/O
I/O/(TCK) (2)
I/O
GND
I/O
Pin 12
Pin 23
44-Pin TQFP
Notes:
(1) The pin functions shown in parenthesis are only available in MAX 7000E and MAX 7000S devices.
(2) JTAG ports are available in MAX 7000S devices only.
Altera Corporation
59