EP1S80F1020C6 Datasheet, PDF (562/864 Pages) Altera Corporation – Stratix Device Handbook, Volume 1

Architecture
1 The output registers form part of the accumulator in the
multiply-accumulate mode.
Routing Structure & Control Signals
This section describes the interface between the DSP blocks and the row
interface blocks. It also describes how the DSP block generates control
signals and how the signals route from the row interface to the DSP block.
DSP Block Interface
The DSP blocks are organized in columns, which provides efficient
horizontal communication between the blocks and the column-based
memory blocks. The DSP block communicates with other parts of the
device through an input and output interface. Each DSP block, including
the input and output interface, is 8 logic array blocks (LABs) long.
The DSP block and row interface blocks consist of eight blocks that
connect to eight adjacent LAB rows on the left and right. Each of the eight
blocks has two regions: right and left, one per row. The DSP block
receives 144 data input signals and 18 control signals for a total of
162 input signals. This block drives out 144 data output signals; 2 of the
data signals can be used as overflow signals (overflow). Figure 6–6
provides an overview of the DSP block and its interface to adjacent LABs.
Figure 6–6. DSP Block Interface to Adjacent LABs
DSP Block & Row Interface
144
8 LAB ₁₆₂
Rows
Row
Interfaces
0 through 7
Data
DSP
Block
144
18
Control
8 LAB
Rows
DSP Block
Input Interface
DSP Block
Output Interface
Input Interface
The DSP block input interface has 162 input signals from adjacent LABs;
18 data signals per row and 18 control signals per block.
Output Interface
The DSP block output interface drives 144 outputs to adjacent LABs, 18
signals per row from 8 rows.
6–12
Stratix Device Handbook, Volume 2
Altera Corporation
July 2005