EP1S80F1020C6 Datasheet, PDF (244/864 Pages) Altera Corporation – Stratix Device Handbook, Volume 1

Timing Model
Table 4–102 shows the reporting methodology used by the Quartus II
software for minimum timing information for output pins.
Table 4–102. Reporting Methodology For Minimum Timing For Single-Ended Output Pins (Part 1 of 2)
Notes (1), (2), (3)
I/O Standard
Loading and Termination
Measurement
Point
R_UP
R_DN
R_S
R_T
Ω
Ω
Ω
Ω
V_CCIO
(V)
VTT
C_L
(V) (pF)
V_MEAS
3.3-V LVTTL
–
–
0
–
3.600 3.600 10
1.800
2.5-V LVTTL
–
–
0
–
2.630 2.630 10
1.200
1.8-V LVTTL
–
–
0
–
1.950 1.950 10
0.880
1.5-V LVTTL
–
–
0
–
1.600 1.600 10
0.750
3.3-V LVCMOS
–
–
0
–
3.600 3.600 10
1.800
2.5-V LVCMOS
–
–
0
–
2.630 2.630 10
1.200
1.8-V LVCMOS
–
–
0
–
1.950 1.950 10
0.880
1.5-V LVCMOS
–
–
0
–
1.600 1.600 10
0.750
3.3-V GTL
–
–
0
25
3.600 1.260 30
0.860
2.5-V GTL
–
–
0
25
2.630 1.260 30
0.860
3.3-V GTL+
–
–
0
25
3.600 1.650 30
1.120
2.5-V GTL+
–
–
0
25
2.630 1.650 30
1.120
3.3-V SSTL-3 Class II
–
–
25 25
3.600 1.750
30
1.750
3.3-V SSTL-3 Class I
–
–
25 50
3.600 1.750
30
1.750
2.5-V SSTL-2 Class II
–
–
25 25
2.630 1.390
30
1.390
2.5-V SSTL-2 Class I
–
–
25 50
2.630 1.390
30
1.390
1.8-V SSTL-18 Class II
–
–
25 25
1.950 1.040
30
1.040
1.8-V SSTL-18 Class I
–
–
25 50
1.950 1.040
30
1.040
1.5-V HSTL Class II
–
–
0
25
1.600 0.800 20
0.900
1.5-V HSTL Class I
–
–
0
50
1.600 0.800 20
0.900
1.8-V HSTL Class II
–
–
0
25
1.950 0.900 20
1.000
1.8-V HSTL Class I
–
–
0
50
1.950 0.900 20
1.000
3.3-V PCI (4)
–/25 25/– 0
–
3.600 1.950 10
1.026/2.214
3.3-V PCI-X 1.0 (4)
–/25 25/– 0
–
3.600 1.950 10
1.026/2.214
3.3-V Compact PCI (4) –/25 25/–
0
–
3.600 3.600 10
1.026/2.214
3.3-V AGP 1× (4)
–/25 25/– 0
–
3.600 3.600 10
1.026/2.214
4–64
Stratix Device Handbook, Volume 1
Altera Corporation
January 2006