EP1S80F1020C6 Datasheet, PDF (357/864 Pages) Altera Corporation – Stratix Device Handbook, Volume 1

General-Purpose PLLs in Stratix & Stratix GX Devices
Table 1–16. Stratix CLK & FPLLCLK Input Pin Connections to Global & Regional Clock Networks Note (1)
CLK Pins
FPLLCLK (2)
Clock Network
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 7 8 9 10
RCLK13
v
RCLK14
v
RCLK15
v
Notes to Table 1–16:
(1) The CLK and FPLLCLK pins cannot drive.
(2) The FPLLCLK pin is only available in EP1S80, EP1S60, EP1S40, and EP1S30 devices.
The fast PLLs also drive high-speed SERDES clocks for differential I/O
interfacing. For information on these FPLLCLK pins, see the High-Speed
Differential I/O Interfaces in Stratix Devices chapter.
Figure 1–21 shows the global and regional clock input and output
connections from the enhanced. Figure 1–21 shows graphically the same
information as Tables 1–15 and 1–16 but with the added detail of where
each specific PLL output port drives to.
Altera Corporation
July 2005
1–47
Stratix Device Handbook, Volume 2