EP1S80F1020C6 Datasheet, PDF (395/864 Pages) Altera Corporation – Stratix Device Handbook, Volume 1

Conclusion
TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices
Figure 2–16. Mixed-Port Read-During-Write: OLD_DATA
inclock
addressA and
addressB
Port A
data_in
A
Address Q
B
Port A
wren
Port B
wren
Port B
data_out
Old
A
B
For mixed-port read-during-write operation of the same address location
of a M-RAM block, the RAM outputs are unknown, as shown in
Figure 2–17.
Figure 2–17. Mixed-Port Read-During-Write: DONT_CARE
inclock
addressA and
addressB
Port A
data_in
A
Address Q
B
Port A
wren
Port B
wren
Port B
data_out
Unknown
B
Mixed-port read-during-write is not supported when two different clocks
are used in a dual-port RAM. The output value will be unknown during
a mixed-port read-during-write operation.
TriMatrix memory, an enhanced RAM architecture with extremely high
memory bandwidth in Stratix and Stratix GX devices, gives advanced
control of memory applications with features such as byte enables, parity
bit storage, and shift-register mode, as well as mixed-port width support
and true dual-port mode.
Altera Corporation
July 2005
2–27
Stratix Device Handbook, Volume 2