EPM7032AETI44-7N Datasheet, PDF (53/64 Pages) Altera Corporation – Programmable Logic Device Family

MAX 7000A Programmable Logic Device Data Sheet
Table 30. EPM7256A Internal Timing Parameters (Part 1 of 2) Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-6
-7
-10
-12
t_IN
t_IO
t_FIN
t_SEXP
t_PEXP
t_LAD
t_LAC
t_IOE
t_OD1
t_OD2
t_OD3
t_ZX1
t_ZX2
t_ZX3
t_XZ
t_SU
t_H
t_FSU
t_FH
t_RD
Min Max Min Max Min Max Min Max
Input pad and buffer delay
I/O input pad and buffer
delay
Fast input delay
Shared expander delay
0.3
0.4
0.5
0.6 ns
0.3
0.4
0.5
0.6 ns
2.4
3.0
3.4
3.8 ns
2.8
3.5
4.7
5.6 ns
Parallel expander delay
0.5
0.6
0.8
1.0 ns
Logic array delay
2.5
3.1
4.2
5.0 ns
Logic control array delay
2.5
3.1
4.2
5.0 ns
Internal output enable
delay
0.2
0.3
0.4
0.5 ns
Output buffer and pad C1 = 35 pF
0.3
delay, slow slew rate = off
V_CCIO = 3.3 V
Output buffer and pad C1 = 35 pF
0.8
delay, slow slew rate = off (5)
V_CCIO = 2.5 V
Output buffer and pad C1 = 35 pF
5.3
delay slow slew rate = on
V_CCIO = 2.5 V or 3.3 V
Output buffer enable
C1 = 35 pF
4.0
delay slow slew rate = off
V_CCIO = 3.3 V
Output buffer enable
C1 = 35 pF
4.5
delay slow slew rate = off (5)
V_CCIO = 2.5 V
Output buffer enable
C1 = 35 pF
9.0
delay slow slew rate = on
V_CCIO = 2.5 V or 3.3 V
Output buffer disable
C1 = 5 pF
4.0
delay
0.4
0.5
0.6 ns
0.9
1.0
1.1 ns
5.4
5.5
5.6 ns
4.0
5.0
5.0 ns
4.5
5.5
5.5 ns
9.0
10.0
10.0 ns
4.0
5.0
5.0 ns
Register setup time
1.0
1.3
1.7
2.0
ns
Register hold time
1.7
2.4
3.7
4.7
ns
Register setup time of fast
input
1.2
1.4
1.4
1.4
ns
Register hold time of fast
input
1.3
1.6
1.6
1.6
ns
Register delay
1.6
2.0
2.7
3.2 ns
Altera Corporation
53