ACEX1K Datasheet, PDF (51/86 Pages) Altera Corporation – Programmable Logic Device Family

ACEX 1K Programmable Logic Device Family Data Sheet
Figure 24 shows the overall timing model, which maps the possible paths
to and from the various elements of the ACEX 1K device.
Figure 24. ACEX 1K Device Timing Model
Dedicated
Clock/Input
Interconnect
I/O Element
Logic
Element
Embedded Array
Block
Figures 25 through 28 show the delays that correspond to various paths
and functions within the LE, IOE, EAB, and bidirectional timing models.
Figure 25. ACEX 1K Device LE Timing Model
Carry-In
Cascade-In
Data-In
Control-In
LUT Delay
t_LUT
t_RLUT
t_CLUT
Packed Register
Delay
t_PACKED
Register Control
Delay
t_C
t_EN
Carry Chain
Delay
t_CGENR
t_CGEN
t_CICO
t_LABCARRY
Carry-Out
Register
Delays
t_CO
t_COMB
t_SU
t_H
t_PRE
t_CLR
t_CASC
t_LABCASC
Cascade-Out
Data-Out
Altera Corporation
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