ACEX1K Datasheet, PDF (39/86 Pages) Altera Corporation – Programmable Logic Device Family

ACEX 1K Programmable Logic Device Family Data Sheet
Table 12. ClockLock & ClockBoost Parameters for -2 Speed-Grade Devices
Symbol
Parameter
Condition
Min Typ Max Unit
t_R
Input rise time
t_F
Input fall time
t_INDUTY Input duty cycle
40
f_CLK1
Input clock frequency (ClockBoost clock
25
multiplication factor equals 1)
f_CLK2
Input clock frequency (ClockBoost clock
16
multiplication factor equals 2)
f_CLKDEV Input deviation from user specification in
the software (1)
t_INCLKSTB Input clock stability (measured between
adjacent clocks)
t_LOCK
Time required for ClockLock or ClockBoost
to acquire lock (3)
t_JITTER
Jitter on ClockLock or ClockBoost-
generated clock (4)
t_INCLKSTB < 100
t_INCLKSTB < 50
t_OUTDUTY Duty cycle for ClockLock or ClockBoost-
40
generated clock
5
ns
5
ns
60
%
80 MHz
40 MHz
25,000 PPM
100
ps
10
µs
250 (4) ps
200 (4) ps
50
60
%
Notes to tables:
(1) To implement the ClockLock and ClockBoost circuitry with the Altera software, designers must specify the input
frequency. The Altera software tunes the PLL in the ClockLock and ClockBoost circuitry to this frequency. The
f_CLKDEV parameter specifies how much the incoming clock can differ from the specified frequency during device
operation. Simulation does not reflect this parameter.
(2) Twenty-five thousand parts per million (PPM) equates to 2.5% of input clock period.
(3) During device configuration, the ClockLock and ClockBoost circuitry is configured before the rest of the device. If
the incoming clock is supplied during configuration, the ClockLock and ClockBoost circuitry locks during
configuration because the t_LOCK value is less than the time required for configuration.
(4) The t_JITTER specification is measured under long-term observation. The maximum value for t_JITTER is 200 ps if
t_INCLKSTB is lower than 50 ps.
I/O
Configuration
This section discusses the PCI pull-up clamping diode option, slew-rate
control, open-drain output option, and MultiVolt I/O interface for
ACEX 1K devices. The PCI pull-up clamping diode, slew-rate control, and
open-drain output options are controlled pin-by-pin via Altera software
logic options. The MultiVolt I/O interface is controlled by connecting
V_CCIO to a different voltage than V_CCINT. Its effect can be simulated in the
Altera software via the Global Project Device Options dialog box (Assign
menu).
Altera Corporation
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