PC28F256P30TFA Datasheet, PDF (47/95 Pages) Micron Technology – Micron Parallel NOR Flash Embedded Memory (P30-65nm)

256Mb and 512Mb (256Mb/256Mb), P30-65nm
Registers
Figure 15: End of Wordline Timing Diagram
CLK
A[Max :1]
DQ [15 :0]
ADV #
OE #
WAIT
Latency Count
Address
Data
Data
Data
EOWL
Table 19: End of Wordline Data and WAIT State Comparison
Latency Count
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
P30-130nm
Data States
WAIT States
Not Supported
Not Supported
4
0 to 1
4
0 to 2
4
0 to 3
4
0 to 4
4
0 to 5
4
0 to 6
Not Supported
Not Supported
P30-65nm
Data States
WAIT States
Not Supported
Not Supported
16
0 to 1
16
0 to 2
16
0 to 3
16
0 to 4
16
0 to 5
16
0 to 6
16
0 to 7
16
0 to 8
16
0 to 9
16
0 to 10
16
0 to 11
16
0 to 12
16
0 to 13
16
0 to 14
WAIT Signal Polarity and Functionality
The WAIT Polarity bit (WP), RCR.10 determines the asserted level (V_OH or V_OL) of WAIT.
When WP is set, WAIT is asserted high (default). When WP is cleared, WAIT is asserted
low. WAIT changes state on valid clock edges during active bus cycles (CE# asserted,
OE# asserted, RST# deasserted).
PDF: 09005aef84566799
p30_65nm_MLC_256Mb-512mb.pdf - Rev. A 1/13 EN
47
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