EPM7256AEFC100-10N Datasheet, PDF (38/64 Pages) Altera Corporation – Programmable Logic Device

MAX 7000A Programmable Logic Device Data Sheet
Table 20. EPM7064AE Internal Timing Parameters (Part 1 of 2) Note (1)
Symbol
Parameter
Conditions
t_IN
t_IO
t_FIN
t_SEXP
t_PEXP
t_LAD
t_LAC
t_IOE
t_OD1
t_OD2
t_OD3
t_ZX1
t_ZX2
t_ZX3
t_XZ
t_SU
t_H
t_FSU
t_FH
t_RD
t_COMB
t_IC
Input pad and buffer delay
I/O input pad and buffer
delay
Fast input delay
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
Output buffer and pad
delay, slow slew rate = off
V_CCIO = 3.3 V
Output buffer and pad
delay, slow slew rate = off
V_CCIO = 2.5 V
Output buffer and pad
delay, slow slew rate = on
V_CCIO = 2.5 V or 3.3 V
Output buffer enable delay,
slow slew rate = off
V_CCIO = 3.3 V
Output buffer enable delay,
slow slew rate = off
V_CCIO = 2.5 V
Output buffer enable delay,
slow slew rate = on
V_CCIO = 3.3 V
Output buffer disable delay
C1 = 35 pF
C1 = 35 pF
(5)
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
(5)
C1 = 35 pF
C1 = 5 pF
Register setup time
Register hold time
Register setup time of fast
input
Register hold time of fast
input
Register delay
Combinatorial delay
Array clock delay
Speed Grade
Unit
-4
-7
-10
Min Max Min Max Min Max
0.6
1.1
1.4 ns
0.6
1.1
1.4 ns
2.5
3.0
3.7 ns
1.8
3.0
3.9 ns
0.4
0.7
0.9 ns
1.5
2.5
3.2 ns
0.6
1.0
1.2 ns
0.0
0.0
0.0 ns
0.8
1.3
1.8 ns
1.3
1.8
2.3 ns
5.8
6.3
6.8 ns
4.0
4.0
5.0 ns
4.5
4.5
5.5 ns
9.0
9.0
10.0 ns
4.0
4.0
5.0 ns
1.3
2.0
2.9
ns
0.6
1.0
1.3
ns
1.0
1.5
1.5
ns
1.5
1.5
1.5
ns
0.7
1.2
1.6 ns
0.6
0.9
1.3 ns
1.2
1.9
2.5 ns
38
Altera Corporation