EPM7256AEFC100-10N Datasheet, PDF (19/64 Pages) Altera Corporation – Programmable Logic Device

MAX 7000A Programmable Logic Device Data Sheet
The programming times described in Tables 5 through 7 are associated
with the worst-case method using the enhanced ISP algorithm.
Table 5. MAX 7000A t_PULSE & Cycle_TCK Values
Device
Programming
EPM7032AE
EPM7064AE
EPM7128AE
EPM7256AE
EPM7512AE
EPM7128A (1)
EPM7256A (1)
t_PPULSE (s)
2.00
2.00
2.00
2.00
2.00
5.11
6.43
Cycle_PTCK
55,000
105,000
205,000
447,000
890,000
832,000
1,603,000
Stand-Alone Verification
t_VPULSE (s)
0.002
0.002
0.002
0.002
0.002
0.03
0.03
Cycle_VTCK
18,000
35,000
68,000
149,000
297,000
528,000
1,024,000
Tables 6 and 7 show the in-system programming and stand alone
verification times for several common test clock frequencies.
Table 6. MAX 7000A In-System Programming Times for Different Test Clock Frequencies
Device
EPM7032AE
EPM7064AE
EPM7128AE
EPM7256AE
EPM7512AE
EPM7128A (1)
EPM7256A (1)
10 MHz
2.01
2.01
2.02
2.05
2.09
5.19
6.59
5 MHz
2.01
2.02
2.04
2.09
2.18
5.27
6.75
2 MHz
2.03
2.05
2.10
2.23
2.45
5.52
7.23
f_TCK
1 MHz 500 kHz 200 kHz 100 kHz
2.06
2.11
2.28
2.55
2.11
2.21
2.53
3.05
2.21
2.41
3.03
4.05
2.45
2.90
4.24
6.47
2.89
3.78
6.45
10.90
5.94
6.77
9.27
13.43
8.03
9.64
14.45 22.46
50 kHz
3.10
4.10
6.10
10.94
19.80
21.75
38.49
Units
s
s
s
s
s
s
s
Altera Corporation
19