EPM7256AEFC100-10N Datasheet, PDF (3/64 Pages) Altera Corporation – Programmable Logic Device

General
Description
MAX 7000A Programmable Logic Device Data Sheet
■ Software design support and automatic place-and-route provided by
Altera’s development systems for Windows-based PCs and Sun
SPARCstation, and HP 9000 Series 700/800 workstations
■ Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Verilog HDL, VHDL, and other interfaces to popular EDA tools from
manufacturers such as Cadence, Exemplar Logic, Mentor Graphics,
OrCAD, Synopsys, Synplicity, and VeriBest
■ Programming support with Altera’s Master Programming Unit
(MPU), MasterBlaster^TM serial/universal serial bus (USB)
communications cable, ByteBlasterMV^TM parallel port download
cable, and BitBlaster^TM serial download cable, as well as
programming hardware from third-party manufacturers and any
Jam^TM STAPL File (.jam), Jam Byte-Code File (.jbc), or Serial Vector
Format File- (.svf) capable in-circuit tester
MAX 7000A (including MAX 7000AE) devices are high-density, high-
performance devices based on Altera’s second-generation MAX
architecture. Fabricated with advanced CMOS technology, the EEPROM-
based MAX 7000A devices operate with a 3.3-V supply voltage and
provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns,
and counter speeds of up to 227.3 MHz. MAX 7000A devices in the -4, -5,
-6, -7, and some -10 speed grades are compatible with the timing
requirements for 33 MHz operation of the PCI Special Interest Group (PCI
SIG) PCI Local Bus Specification, Revision 2.2. See Table 2.
Table 2. MAX 7000A Speed Grades
Device
Speed Grade
-4
-5
-6
-7
-10
-12
EPM7032AE
v
v
v
EPM7064AE
v
v
v
EPM7128A
EPM7128AE
v
v
v
v
v
v
v
EPM7256A
EPM7256AE
v
v
v
v
v
v
v
EPM7512AE
v
v
v
Altera Corporation
3