EPM7256AEFC100-10N Datasheet, PDF (34/64 Pages) Altera Corporation – Programmable Logic Device

MAX 7000A Programmable Logic Device Data Sheet
Tables 17 through 30 show EPM7032AE, EPM7064AE, EPM7128AE,
EPM7256AE, EPM7512AE, EPM7128A, and EPM7256A timing
information.
Table 17. EPM7032AE External Timing Parameters Note (1)
Symbol
Parameter
Conditions
-4
Min Max
t_PD1
Input to non-registered
C1 = 35 pF (2)
4.5
output
t_PD2
I/O input to non-registered C1 = 35 pF (2)
4.5
output
t_SU
Global clock setup time (2)
2.9
t_H
Global clock hold time
(2)
0.0
t_FSU
Global clock setup time of
2.5
fast input
t_FH
Global clock hold time of
0.0
fast input
t_CO1
Global clock to output delay C1 = 35 pF
1.0 3.0
t_CH
Global clock high time
2.0
t_CL
Global clock low time
2.0
t_ASU
Array clock setup time
(2)
1.6
t_AH
Array clock hold time
(2)
0.3
t_ACO1 Array clock to output delay C1 = 35 pF (2) 1.0 4.3
t_ACH
Array clock high time
2.0
t_ACL
Array clock low time
2.0
t_CPPW Minimum pulse width for (3)
2.0
clear and preset
t_CNT
Minimum global clock
(2)
4.4
period
f_CNT
Maximum internal global
clock frequency
(2), (4)
227.3
t_ACNT
f_ACNT
Minimum array clock period (2)
Maximum internal array (2), (4)
clock frequency
4.4
227.3
Speed Grade
-7
Min Max
7.5
-10
Min Max
10
7.5
10
4.7
6.3
0.0
0.0
3.0
3.0
0.0
0.0
1.0 5.0 1.0 6.7
3.0
4.0
3.0
4.0
2.5
3.6
0.5
0.5
1.0 7.2 1.0 9.4
3.0
4.0
3.0
4.0
3.0
4.0
7.2
9.7
138.9
103.1
7.2
9.7
138.9
103.1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
MHz
34
Altera Corporation