ACEX1K_03 Datasheet, PDF (38/86 Pages) Altera Corporation – Programmable Logic Device Family

ACEX 1K Programmable Logic Device Family Data Sheet
Tables 11 and 12 summarize the ClockLock and ClockBoost parameters
for -1 and -2 speed-grade devices, respectively.
Table 11. ClockLock & ClockBoost Parameters for -1 Speed-Grade Devices
Symbol
Parameter
Condition
Min
t_R
Input rise time
t_F
Input fall time
t_INDUTY Input duty cycle
40
f_CLK1
Input clock frequency (ClockBoost clock
25
multiplication factor equals 1)
f_CLK2
Input clock frequency (ClockBoost clock
16
multiplication factor equals 2)
f_CLKDEV Input deviation from user specification in the
Altera software (1)
t_INCLKSTB Input clock stability (measured between
adjacent clocks)
t_LOCK
Time required for ClockLock or ClockBoost
to acquire lock (3)
t_JITTER
Jitter on ClockLock or ClockBoost-
generated clock (4)
t_INCLKSTB <100
t_INCLKSTB < 50
t_OUTDUTY Duty cycle for ClockLock or ClockBoost-
40
generated clock
Typ Max Unit
5
ns
5
ns
60
%
180 MHz
90
MHz
25,000
(2)
100
PPM
ps
10
µs
250 (4) ps
200 (4) ps
50
60
%
38
Altera Corporation