ACEX1K_03 Datasheet, PDF (10/86 Pages) Altera Corporation – Programmable Logic Device Family

ACEX 1K Programmable Logic Device Family Data Sheet
Figure 2. ACEX 1K Device in Dual-Port RAM Mode
Dedicated Inputs &
Global Signals
Dedicated Clocks
Note (1)
Row Interconnect
data[ ]
2
4
rdaddress[ ]
EAB Local
Interconnect (2)
wraddress[ ]
rden
DQ
ENA
DQ
ENA
DQ
ENA
RAM/ROM
256 × 16
Data
In
512
1,024
×
×
8
4
2,048 × 2
Data Out
Read Address
4, 8, 16, 32
DQ
4, 8
ENA
Write Address
4, 8, 16, 32
wren
outclocken
DQ
ENA
Read Enable
Write Enable
inclocken
inclock
outclock
DQ
ENA
Write
Pulse
Generator
Multiplexers allow read
address and read
enable registers to be
clocked by inclock or
outclock signals.
Column Interconnect
Notes:
(1) All registers can be asynchronously cleared by EAB local interconnect signals, global signals, or the chip-wide reset.
(2) EP1K10, EP1K30, and EP1K50 devices have 88 EAB local interconnect channels; EP1K100 devices have 104 EAB
local interconnect channels.
The EAB can use Altera megafunctions to implement dual-port RAM
applications where both ports can read or write, as shown in Figure 3. The
ACEX 1K EAB can also be used in a single-port mode (see Figure 4).
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Altera Corporation