EPM3256ATI144-10 Datasheet, PDF (35/46 Pages) Altera Corporation – Programmable Logic Device Family

MAX 3000A Programmable Logic Device Family Data Sheet
Table 22. EPM3256A External Timing Parameters Note (1)
Symbol
Parameter
Conditions
t_CNT
f_CNT
t_ACNT
f_ACNT
Minimum global clock
period
Maximum internal global
clock frequency
Minimum array clock
period
Maximum internal array
clock frequency
(2)
(2), (4)
(2)
(2), (4)
Speed Grade
–7
–10
Min
Max
Min
Max
7.9
10.5
126.6
95.2
7.9
10.5
126.6
95.2
Unit
ns
MHz
ns
MHz
Table 23. EPM3256A Internal Timing Parameters (Part 1 of 2) Note (1)
Symbol
Parameter
Conditions
t_IN
t_IO
t_SEXP
t_PEXP
t_LAD
t_LAC
t_IOE
t_OD1
t_OD2
t_OD3
t_ZX1
t_ZX2
Input pad and buffer delay
I/O input pad and buffer delay
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
Output buffer and pad delay,
slow slew rate = off
V_CCIO = 3.3 V
Output buffer and pad delay,
slow slew rate = off
V_CCIO = 2.5 V
Output buffer and pad delay,
slow slew rate = on
V_CCIO = 2.5 V or 3.3 V
Output buffer enable delay, slow
slew rate = off V_CCIO = 3.3 V
Output buffer enable delay, slow
slew rate = off V_CCIO = 2.5 V
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
Speed Grade
Unit
–7
–10
Min Max Min Max
0.9
1.2
ns
0.9
1.2
ns
2.8
3.7
ns
0.5
0.6
ns
2.2
2.8
ns
1.0
1.3
ns
0.0
0.0
ns
1.2
1.6
ns
1.7
2.1
ns
6.2
6.6
ns
4.0
5.0
ns
4.5
5.5
ns
Altera Corporation
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