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EPM3256ATI144-10 Datasheet, PDF (13/46 Pages) Altera Corporation – Programmable Logic Device Family | |||
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MAX 3000A Programmable Logic Device Family Data Sheet
InâSystem
Programma-
bility
MAX 3000A devices can be programmed inâsystem via an industryâ
standard fourâpin IEEE Std. 1149.1-1990 (JTAG) interface. In-system
programmability (ISP) offers quick, efficient iterations during design
development and debugging cycles. The MAX 3000A architecture
internally generates the high programming voltages required to program
its EEPROM cells, allowing inâsystem programming with only a single
3.3âV power supply. During inâsystem programming, the I/O pins are
triâstated and weakly pulledâup to eliminate board conflicts. The pullâup
value is nominally 50 kΩ.
MAX 3000A devices have an enhanced ISP algorithm for faster
programming. These devices also offer an ISP_Done bit that ensures safe
operation when inâsystem programming is interrupted. This ISP_Done
bit, which is the last bit programmed, prevents all I/O pins from driving
until the bit is programmed.
ISP simplifies the manufacturing flow by allowing devices to be mounted
on a printed circuit board (PCB) with standard pickâandâplace equipment
before they are programmed. MAX 3000A devices can be programmed by
downloading the information via inâcircuit testers, embedded processors,
the MasterBlaster communications cable, the ByteBlasterMV parallel port
download cable, and the BitBlaster serial download cable. Programming
the devices after they are placed on the board eliminates lead damage on
highâpinâcount packages (e.g., QFP packages) due to device handling.
MAX 3000A devices can be reprogrammed after a system has already
shipped to the field. For example, product upgrades can be performed in
the field via software or modem.
f
The Jam STAPL programming and test language can be used to program
MAX 3000A devices with inâcircuit testers, PCs, or embedded processors.
For more information on using the Jam STAPL programming and test
language, see Application Note 88 (Using the Jam Language for ISP & ICR via
an Embedded Processor), Application Note 122 (Using Jam STAPL for ISP &
ICR via an Embedded Processor) and AN 111 (Embedded Programming Using
the 8051 and Jam Byte-Code).
The ISP circuitry in MAX 3000A devices is compliant with the IEEE Std.
1532 specification. The IEEE Std. 1532 is a standard developed to allow
concurrent ISP between multiple PLD vendors.
Altera Corporation
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