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EPM3256ATI144-10 Datasheet, PDF (32/46 Pages) Altera Corporation – Programmable Logic Device Family | |||
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MAX 3000A Programmable Logic Device Family Data Sheet
Table 19. EPM3064A Internal Timing Parameters (Part 2 of 2) Note (1)
Symbol
Parameter
tCLR
Register clear time
tPIA
PIA delay
tLPA
Lowâpower adder
Conditions
(2)
(5)
Speed Grade
Unit
â4
â7
â10
Min Max Min Max Min Max
1.3
2.1
2.9 ns
1.0
1.7
2.3 ns
3.5
4.0
5.0 ns
Table 20. EPM3128A External Timing Parameters Note (1)
Symbol
Parameter
Conditions
â5
Min Max
tPD1
Input to nonâ
C1 = 35 pF
5.0
registered output
(2)
tPD2
I/O input to nonâ
C1 = 35 pF
5.0
registered output
(2)
tSU
Global clock setup (2)
3.3
time
tH
Global clock hold time (2)
0.0
tCO1
Global clock to output C1 = 35 pF 1.0
3.4
delay
tCH
Global clock high time
2.0
tCL
Global clock low time
2.0
tASU
Array clock setup time (2)
1.8
tAH
Array clock hold time (2)
0.2
tACO1 Array clock to output C1 = 35 pF 1.0
4.9
delay
(2)
tACH
Array clock high time
2.0
tACL
Array clock low time
2.0
tCPPW Minimum pulse width (3)
2.0
for clear and preset
tCNT
Minimum global clock (2)
5.2
period
fCNT
Maximum internal
(2), (4)
global clock frequency
192.3
tACNT Minimum array clock (2)
5.2
period
Speed Grade
â7
Min Max
7.5
7.5
4.9
0.0
1.0
5.0
3.0
3.0
2.8
0.3
1.0
7.1
3.0
3.0
3.0
7.7
129.9
7.7
Unit
â10
Min Max
10 ns
10 ns
6.6
ns
0.0
ns
1.0
6.6 ns
4.0
ns
4.0
ns
3.8
ns
0.4
ns
1.0
9.4 ns
4.0
ns
4.0
ns
4.0
ns
10.2 ns
98.0
MHz
10.2 ns
32
Altera Corporation
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