EPM3256ATI144-10 Datasheet, PDF (21/46 Pages) Altera Corporation – Programmable Logic Device Family

MAX 3000A Programmable Logic Device Family Data Sheet
Open–Drain Output Option
MAX 3000A devices provide an optional open–drain (equivalent to
open-collector) output for each I/O pin. This open–drain output enables
the device to provide system–level control signals (e.g., interrupt and
write enable signals) that can be asserted by any of several devices. It can
also provide an additional wired–OR plane.
Open-drain output pins on MAX 3000A devices (with a pull-up resistor to
the 5.0-V supply) can drive 5.0-V CMOS input pins that require a high V_IH.
When the open-drain pin is active, it will drive low. When the pin is
inactive, the resistor will pull up the trace to 5.0 V, thereby meeting CMOS
requirements. The open-drain pin will only drive low or tri-state; it will
never drive high. The rise time is dependent on the value of the pull-up
resistor and load impedance. The I_OL current specification should be
considered when selecting a pull-up resistor
Design Security
Generic Testing
Slew–Rate Control
The output buffer for each MAX 3000A I/O pin has an adjustable output
slew rate that can be configured for low–noise or high–speed
performance. A faster slew rate provides high–speed transitions for
high-performance systems. However, these fast transitions may introduce
noise transients into the system. A slow slew rate reduces system noise,
but adds a nominal delay of 4 to 5 ns. When the configuration cell is
turned off, the slew rate is set for low–noise performance. Each I/O pin
has an individual EEPROM bit that controls the slew rate, allowing
designers to specify the slew rate on a pin–by–pin basis. The slew rate
control affects both the rising and falling edges of the output signal.
All MAX 3000A devices contain a programmable security bit that controls
access to the data programmed into the device. When this bit is
programmed, a design implemented in the device cannot be copied or
retrieved. This feature provides a high level of design security because
programmed data within EEPROM cells is invisible. The security bit that
controls this function, as well as all other programmed data, is reset only
when the device is reprogrammed.
MAX 3000A devices are fully tested. Complete testing of each
programmable EEPROM bit and all internal logic elements ensures 100%
programming yield. AC test measurements are taken under conditions
equivalent to those shown in Figure 8. Test patterns can be used and then
erased during early stages of the production flow.
Altera Corporation
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