EPM3064ATC100-7N Datasheet, PDF (33/46 Pages) Altera Corporation – Programmable Logic Device Family

MAX 3000A Programmable Logic Device Family Data Sheet
Table 20. EPM3128A External Timing Parameters Note (1)
Symbol
Parameter
Conditions
f_ACNT
Maximum internal
(2), (4)
array clock frequency
–5
Min Max
192.3
Speed Grade
–7
Min Max
129.9
Unit
–10
Min Max
98.0
MHz
Table 21. EPM3128A Internal Timing Parameters (Part 1 of 2) Note (1)
Symbol
Parameter
Conditions
t_IN
t_IO
t_SEXP
t_PEXP
t_LAD
t_LAC
t_IOE
t_OD1
t_OD2
t_OD3
t_ZX1
t_ZX2
t_ZX3
t_XZ
Input pad and buffer delay
I/O input pad and buffer
delay
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
Output buffer and pad
delay, slow slew rate = off
V_CCIO = 3.3 V
Output buffer and pad
delay, slow slew rate = off
V_CCIO = 2.5 V
Output buffer and pad
delay, slow slew rate = on
V_CCIO = 2.5 V or 3.3 V
Output buffer enable delay,
slow slew rate = off
V_CCIO = 3.3 V
Output buffer enable delay,
slow slew rate = off
V_CCIO = 2.5 V
Output buffer enable delay,
slow slew rate = on
V_CCIO = 2.5 V or 3.3 V
Output buffer disable delay
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 5 pF
Speed Grade
Unit
–5
–7
–10
Min Max Min Max Min Max
0.7
1.0
1.4 ns
0.7
1.0
1.4 ns
2.0
2.9
3.8 ns
0.4
0.7
0.9 ns
1.6
2.4
3.1 ns
0.7
1.0
1.3 ns
0.0
0.0
0.0 ns
0.8
1.2
1.6 ns
1.3
1.7
2.1 ns
5.8
6.2
6.6 ns
4.0
4.0
5.0 ns
4.5
4.5
5.5 ns
9.0
9.0
10.0 ns
4.0
4.0
5.0 ns
Altera Corporation
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