EPM3064ATC100-7N Datasheet, PDF (32/46 Pages) Altera Corporation – Programmable Logic Device Family

MAX 3000A Programmable Logic Device Family Data Sheet
Table 19. EPM3064A Internal Timing Parameters (Part 2 of 2) Note (1)
Symbol
Parameter
t_CLR
Register clear time
t_PIA
PIA delay
t_LPA
Low–power adder
Conditions
(2)
(5)
Speed Grade
Unit
–4
–7
–10
Min Max Min Max Min Max
1.3
2.1
2.9 ns
1.0
1.7
2.3 ns
3.5
4.0
5.0 ns
Table 20. EPM3128A External Timing Parameters Note (1)
Symbol
Parameter
Conditions
–5
Min Max
t_PD1
Input to non–
C1 = 35 pF
5.0
registered output
(2)
t_PD2
I/O input to non–
C1 = 35 pF
5.0
registered output
(2)
t_SU
Global clock setup (2)
3.3
time
t_H
Global clock hold time (2)
0.0
t_CO1
Global clock to output C1 = 35 pF 1.0
3.4
delay
t_CH
Global clock high time
2.0
t_CL
Global clock low time
2.0
t_ASU
Array clock setup time (2)
1.8
t_AH
Array clock hold time (2)
0.2
t_ACO1 Array clock to output C1 = 35 pF 1.0
4.9
delay
(2)
t_ACH
Array clock high time
2.0
t_ACL
Array clock low time
2.0
t_CPPW Minimum pulse width (3)
2.0
for clear and preset
t_CNT
Minimum global clock (2)
5.2
period
f_CNT
Maximum internal
(2), (4)
global clock frequency
192.3
t_ACNT Minimum array clock (2)
5.2
period
Speed Grade
–7
Min Max
7.5
7.5
4.9
0.0
1.0
5.0
3.0
3.0
2.8
0.3
1.0
7.1
3.0
3.0
3.0
7.7
129.9
7.7
Unit
–10
Min Max
10 ns
10 ns
6.6
ns
0.0
ns
1.0
6.6 ns
4.0
ns
4.0
ns
3.8
ns
0.4
ns
1.0
9.4 ns
4.0
ns
4.0
ns
4.0
ns
10.2 ns
98.0
MHz
10.2 ns
32
Altera Corporation