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EPM3064ATC100-7N Datasheet, PDF (15/46 Pages) Altera Corporation – Programmable Logic Device Family | |||
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MAX 3000A Programmable Logic Device Family Data Sheet
By combining the pulse and shift times for each of the programming
stages, the program or verify time can be derived as a function of the TCK
frequency, the number of devices, and specific target device(s). Because
different ISP-capable devices have a different number of EEPROM cells,
both the total fixed and total variable times are unique for a single device.
Programming a Single MAX 3000A Device
The time required to program a single MAX 3000A device in-system can
be calculated from the following formula:
tPROG
=
tPPUL
S
E
+
C-----y---c---l---e--P----T----C-----K--
fTCK
where: tPROG
tPPULSE
CyclePTCK
fTCK
= Programming time
= Sum of the fixed times to erase, program, and
verify the EEPROM cells
= Number of TCK cycles to program a device
= TCK frequency
The ISP times for a stand-alone verification of a single MAX 3000A device
can be calculated from the following formula:
tVER
=
tVP
UL
S
E
+
-C----y---c---l--e---V-----T----C----K---
fTCK
where: tVER
= Verify time
tVPULSE = Sum of the fixed times to verify the EEPROM cells
CycleVTCK = Number of TCK cycles to verify a device
Altera Corporation
15
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