EPM3064ATC100-7N Datasheet, PDF (30/46 Pages) Altera Corporation – Programmable Logic Device Family

MAX 3000A Programmable Logic Device Family Data Sheet
Table 17. EPM3032A Internal Timing Parameters (Part 2 of 2) Note (1)
Symbol
Parameter
t_PIA
PIA delay
t_LPA
Low–power adder
Conditions
(2)
(5)
Speed Grade
Unit
–4
–7
–10
Min Max Min Max Min Max
0.9
1.5
2.1 ns
2.5
4.0
5.0 ns
Table 18. EPM3064A External Timing Parameters Note (1)
Symbol
Parameter
Conditions
–4
t_PD1
t_PD2
t_SU
t_H
t_CO1
t_CH
t_CL
t_ASU
t_AH
t_ACO1
t_ACH
t_ACL
t_CPPW
t_CNT
f_CNT
t_ACNT
f_ACNT
Min Max
Input to non–registered C1 = 35 pF (2)
4.5
output
I/O input to non–registered C1 = 35 pF (2)
4.5
output
Global clock setup time (2)
2.8
Global clock hold time
(2)
0.0
Global clock to output delay C1 = 35 pF
1.0 3.1
Global clock high time
2.0
Global clock low time
2.0
Array clock setup time
(2)
1.6
Array clock hold time
(2)
0.3
Array clock to output delay C1 = 35 pF (2) 1.0 4.3
Array clock high time
2.0
Array clock low time
2.0
Minimum pulse width for (3)
2.0
clear and preset
Minimum global clock
(2)
4.5
period
Maximum internal global
clock frequency
(2), (4)
222.2
Minimum array clock period (2)
4.5
Maximum internal array
clock frequency
(2), (4)
222.2
Speed Grade
–7
Min Max
7.5
–10
Min Max
10.0
7.5
10.0
4.7
6.2
0.0
0.0
1.0 5.1 1.0 7.0
3.0
4.0
3.0
4.0
2.6
3.6
0.4
0.6
1.0 7.2 1.0 9.6
3.0
4.0
3.0
4.0
3.0
4.0
7.4
10.0
135.1
100.0
7.4
10.0
135.1
100.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
MHz
30
Altera Corporation