EPM3032ATC44-10N Datasheet, PDF (26/46 Pages) Altera Corporation – Programmable Logic Device Family

MAX 3000A Programmable Logic Device Family Data Sheet
Timing Model
MAX 3000A device timing can be analyzed with the Altera software, with
a variety of popular industry–standard EDA simulators and timing
analyzers, or with the timing model shown in Figure 10. MAX 3000A
devices have predictable internal delays that enable the designer to
determine the worst–case timing of any design. The software provides
timing simulation, point–to–point delay prediction, and detailed timing
analysis for device–wide performance evaluation.
Figure 10. MAX 3000A Timing Model
Input
Delay
t_IN
PIA
Delay
t _PIA
Internal Output
Enable Delay
t _IOE
Global Control
Delay
t _GLOB
Logic Array
Delay
t _LAD
Register
Control Delay
t _LAC
t_IC
t _EN
Shared
Expander Delay
t _SEXP
Parallel
Expander Delay
t _PEXP
Register
Delay
t _SU
t_H
t _PRE
t _CLR
t _RD
t _COMB
Output
Delay
t _OD1
t _OD2
t _OD3
t _XZ
t _{Z X1}
t _{Z X2}
t _{Z X3}
I/O
Delay
t_{I O}
The timing characteristics of any signal path can be derived from the
timing model and parameters of a particular device. External timing
parameters, which represent pin–to–pin timing delays, can be calculated
as the sum of internal parameters. Figure 11 shows the timing relationship
between internal and external delay parameters.
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Altera Corporation