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EPM3032ATC44-10N Datasheet, PDF (2/46 Pages) Altera Corporation – Programmable Logic Device Family | |||
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MAX 3000A Programmable Logic Device Family Data Sheet
...and More
Features
General
Description
â PCI compatible
â Busâfriendly architecture including programmable slewârate control
â Openâdrain output option
â Programmable macrocell flipflops with individual clear, preset,
clock, and clock enable controls
â Programmable powerâsaving mode for a power reduction of over
50% in each macrocell
â Configurable expander productâterm distribution, allowing up to
32 product terms per macrocell
â Programmable security bit for protection of proprietary designs
â Enhanced architectural features, including:
â 6 or 10 pinâ or logicâdriven output enable signals
â Two global clock signals with optional inversion
â Enhanced interconnect resources for improved routability
â Programmable output slewârate control
â Software design support and automatic placeâandâroute provided
by Alteraâs development systems for Windowsâbased PCs and Sun
SPARCstations, and HP 9000 Series 700/800 workstations
â Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Verilog HDL, VHDL, and other interfaces to popular EDA tools from
thirdâparty manufacturers such as Cadence, Exemplar Logic, Mentor
Graphics, OrCAD, Synopsys, Synplicity, and VeriBest
â Programming support with the Altera master programming unit
(MPU), MasterBlasterTM communications cable, ByteBlasterMVTM
parallel port download cable, BitBlasterTM serial download cable as
well as programming hardware from thirdâparty manufacturers and
any inâcircuit tester that supports JamTM Standard Test and
Programming Language (STAPL) Files (.jam), Jam STAPL Byte-Code
Files (.jbc), or Serial Vector Format Files (.svf)
MAX 3000A devices are lowâcost, highâperformance devices based on the
Altera MAX architecture. Fabricated with advanced CMOS technology,
the EEPROMâbased MAX 3000A devices operate with a 3.3-V supply
voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as
fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 3000A devices
in the â4, â5, â6, â7, and â10 speed grades are compatible with the timing
requirements of the PCI Special Interest Group (PCI SIG) PCI Local Bus
Specification, Revision 2.2. See Table 2.
2
Altera Corporation
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