ER2120QI Datasheet, PDF (23/24 Pages) Altera Corporation – 2A Synchronous Buck Regulator with Integrated MOSFETs

Page 23
In order to dissipate heat generated by the internal V_TT LDO, the ground pad, pin 29, should be connected to the internal ground
plane through at least five vias. This allows heat to move away from the IC and also ties the pad to the ground plane through a low
impedance path.
The switching components should be placed close to the ER2120QI first. Minimize the length of connections between the input
capacitors, C_IN, and the power switches by placing them nearby. Position both the ceramic and bulk input capacitors as close to the
upper MOSFET drain as possible. Position the output inductor and output capacitors between the upper and lower MOSFETs and
the load. Make the PGND and the output capacitors as short as possible.
The critical small signal components include any bypass capacitors, feedback components, and compensation components. Place
the PWM converter compensation components close to the FB and COMP pins. The feedback resistors should be located as close
as possible to the FB pin, with vias tied straight to the ground plane as required.
5V
AVINO
PVIN
C_BP1
R_BP
ER2120QI
AVIN
SW
C_BP2
PGND
COMP
FB
V_IN
C_IN
L₁
V_OUT1
C_OUT1
C₂
R₂
C₁
R₁
R₄
C_{3 R3}
GND PAD
KEY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT AND/OR POWER PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 38. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS
Document Revision History
The table lists the revision history for this document.
Date
March 2014
Version
1.0 Initial release.
Changes
March 2014 Altera Corporation
09615
ER2120QI 2A Synchronous Buck Regulator with Integrated MOSFETs
March 14, 2014
Rev A