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ER2120QI Datasheet, PDF (19/24 Pages) Altera Corporation – 2A Synchronous Buck Regulator with Integrated MOSFETs
Page 19
VOUT
DVHUMP
DVESR
DVSAG
DVESL
IOUT
ITRAN
FIGURE 35. TYPICAL TRANSIENT RESPONSE
After the initial spike, attributable to the ESR and ESL of the capacitors, the output voltage experiences sag. This sag is a direct
consequence of the amount of capacitance on the output.
During removal of the same output load, the energy stored in the inductor is dumped into the output capacitors. This energy dumping
creates a temporary hump in the output voltage. This hump, as with the sag, can be attributed to the total amount of capacitance on the
output. Figure 35 shows a typical response to a load transient.
The amplitudes of the different types of voltage excursions can be approximated using Equation 5.
VESR = ESR  Itran
VESL = ESL  -d---I--dt--r--ta----n-
VSAG = -C----o---u-L---t-o---u----t-V-----i-In--t--r-–-a---nV---2-o----u---t--
VHUMP = L-C---o--o-u--u--t--t-----I--tV--r--ao---n-u--2-t-
(EQ. 5)
where: Itran = Output Load Current Transient, and Cout = Total Output Capacitance.
In a typical converter design, the ESR of the output capacitor bank dominates the transient response. The ESR and ESL typically
are the major contributing factors in determining the output capacitance. The number of output capacitors can be determined by
using Equation 6, which relates the ESR and ESL of the capacitors to the transient load step and the voltage limit (DVo):
Number of Capacitors = --E--------S---------L-----------d------t--d------I----t----r----a--------n----V-+---o--E-----S----R----------I--t--r--a---n--
(EQ. 6)
If DVSAG or DVHUMP is found to be too large for the output voltage limits, then the amount of capacitance may need to be
increased. In this situation, a trade-off between output inductance and output capacitance may be necessary.
The ESL of the capacitors, which is an important parameter in the previous equations, is not usually listed in databooks.
Practically, it can be approximated using Equation 7 if an Impedance vs Frequency curve is given for a specific capacitor:
ESL = C--------2-----------1-------f--r--e---s------2-
(EQ. 7)
where fres is the frequency at which the lowest impedance is achieved (resonant frequency).
The ESL of the capacitors becomes a concern when designing circuits that supply power to loads with high rates of change in the
current.
March 2014 Altera Corporation
09615
ER2120QI 2A Synchronous Buck Regulator with Integrated MOSFETs
March 14, 2014
Rev A