ER2120QI Datasheet, PDF (22/24 Pages) Altera Corporation – 2A Synchronous Buck Regulator with Integrated MOSFETs

Page 22
Compensation Break Frequency Equations
f_Z1 = -2---_------x-----R--1--₂------x-----C----₁-
f_Z2 = -2---_------x-----_--R-----₁----+-1----R-----₃---_----x------C----₃-
f_P1
=
---------------------------1-----------------------------
2
x
R₂
x



C-C----_{11-----+x-----CC----2-2-}
f_P2 = -2---_------x-----R--1--₃-----x------C----₃-
(EQ. 12)
Figure 37 shows an asymptotic plot of the DC/DC converter gain vs frequency. The actual modulator gain has a high gain peak due
to the high Q factor of the output filter and is not shown in Figure 37. Using the guidelines provided should give a compensation
gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain
at F_P2 with the capabilities of the error amplifier. The closed loop gain is constructed on the graph of Figure 37 by adding the
modulator gain (in dB) to the compensation gain (in dB). This is equivalent to multiplying the modulator transfer function to the
compensation transfer function and plotting the gain.
The compensation gain uses external impedance networks, Z_FB and Z_IN, to provide a stable, high bandwidth (BW) overall loop. A
stable control loop has a gain crossing with -20dB/decade slope and a phase margin greater than +45°. Include worst-case
component variations when determining phase margin.
100
f_Z1 f_Z2
f_P1
f_P2
80
60
OPEN LOOP
ERROR AMP GAIN
40 _20LOG
20 ^(R2^/R1⁾
20LOG
0
(V_IN/V_OSC)
-20
MODULATOR
GAIN
-40
-60 ₁₀
100
f_LC
f_ESR
1k
10k 100k
COMPENSATION
GAIN
CLOSED LOOP
GAIN
1M 10M
FREQUENCY (Hz)
FIGURE 37. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Layout Considerations
Layout is very important in high frequency switching converter design. With power devices switching efficiently between 500kHz
and 1.2MHz, the resulting current transitions from one device to another cause voltage spikes across the interconnecting
impedances and parasitic circuit elements. These voltage spikes can degrade efficiency, radiate noise into the circuit, and lead to
device overvoltage stress. Careful component layout and printed circuit board design minimize these voltage spikes.
As an example, consider the turn-off transition of the control MOSFET. Prior to turn-off, the MOSFET is carrying the full load
current. During turn-off, current stops flowing in the MOSFET and is picked up by the lower MOSFET. Any parasitic inductance
in the switched current path generates a large voltage spike during the switching interval. Careful component selection, tight layout
of the critical components, and short, wide traces minimize the magnitude of voltage spikes.
There are two sets of critical components in the ER2120QI switching converter. The switching components are the most critical
because they switch large amounts of energy and therefore tend to generate large amounts of noise. Next are the small signal
components, which connect to sensitive nodes or supply critical bypass current and signal coupling.
A multi-layer printed circuit board is recommended. Figure 38 shows the connections of the critical components in the converter.
Note that capacitors C_IN and C_OUT could each represent numerous physical capacitors. Dedicate one solid layer (usually a middle
layer of the PC board) for a ground plane, and make all critical component ground connections with vias to this layer. Dedicate
another solid layer as a power plane, and break this plane into smaller islands of common voltage levels. Keep the metal runs from
the SW terminals to the output inductor short. The power plane should support the input power and output power nodes. Use
copper-filled polygons on the top and bottom circuit layers for the phase nodes. Use the remaining printed circuit layers for small
signal wiring. The wiring traces from the GATE pins to the MOSFET gates should be kept short and wide enough to easily handle
the 1A of drive current.
ER2120QI 2A Synchronous Buck Regulator with Integrated MOSFETs
09615
March 14, 2014
March 2014 Altera Corporation
Rev A