ER2120QI Datasheet, PDF(21/24 Page) Altera Corporation – 2A Synchronous Buck Regulator with Integrated MOSFETs

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

ER2120QI Datasheet, PDF (21/24 Pages) Altera Corporation – 2A Synchronous Buck Regulator with Integrated MOSFETs

◁

Page 21

ï VOSC

OSC

PWM

COMPARATOR

DRIVER

VIN

VOUT

ZFB

VE/A

ERROR

AMP

ZIN

REFERENCE

ESR

(PARASITIC)

DETAILED COMPENSATION COMPONENTS

ZFB

VOUT

ZIN

COMP

ER2120QI

REFERENCE

VOUT

0.6

ï´

ï¦

ï§

ï¨

R-R----14- ï¸ï·ï¶

FIGURE 36. VOLTAGE-MODE BUCK CONVERTER COMPENSATION

DESIGN AND OUTPUT VOLTAGE SELECTION

Modulator Break Frequency Equations

fLC=

--------------------1----------------------

2ï° x LO x CO

fESR= 2----ï°------x-----E----S--1---R------x-----C-----O---

(EQ. 11)

The compensation network consists of the error amplifier (internal to the ER2120QI) and the impedance networks, ZIN and ZFB.

The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency (f0dB)

and adequate phase margin. Phase margin is the difference between the closed loop phase at f0dB and 180 degrees. Equation 12

relates the compensation networkâs poles, zeros, and gain to the components (R1, R2, R3, C1, C2 and C3) in Figure 36. Use these

guidelines for locating the poles and zeros of the compensation network:

1. Pick Gain (R2/R1) for desired converter bandwidth.

2. Place first zero below filterâs double pole (~75% FLC).

3. Place second zero at filterâs double pole.

4. Place first pole at ESR Zero.

5. Place second pole at half the switching frequency.

6. Check gain against error amplifierâs open-loop gain.

7. Estimate phase margin; repeat if necessary.

March 2014 Altera Corporation

09615

ER2120QI 2A Synchronous Buck Regulator with Integrated MOSFETs

March 14, 2014

Rev A

▷