EPM9560RC240-15 Datasheet, PDF (22/46 Pages) Altera Corporation – Programmable Logic Device Family

MAX 9000 Programmable Logic Device Family Data Sheet
The programming times described in Tables 7 through 9 are associated
with the worst-case method using the ISP algorithm.
Table 7. MAX 9000 t_PULSE & Cycle_TCK Values
Device
Programming
EPM9320
EPM9320A
EPM9400
EPM9480
EPM9560
EPM9560A
t_PPULSE (s)
11.79
12.00
12.21
12.42
Cycle_PTCK
2,966,000
3,365,000
3,764,000
4,164,000
Stand-Alone Verification
t_VPULSE (s)
0.15
Cycle_VTCK
1,806,000
0.15
2,090,000
0.15
2,374,000
0.15
2,658,000
Tables 8 and 9 show the in-system programming and stand alone
verification times for several common test clock frequencies.
Table 8. MAX 9000 In-System Programming Times for Different Test Clock Frequencies
Device
EPM9320
EPM9320A
EPM9400
EPM9480
EPM9560
EPM9560A
10 MHz 5 MHz
12.09 12.38
2 MHz
13.27
f_TCK
1 MHz 500 kHz 200 kHz 100 kHz
14.76 17.72 26.62 41.45
50 kHz
71.11
Units
s
12.34 12.67 13.68 15.37 18.73 28.83 45.65 79.30
s
12.59 12.96 14.09 15.98 19.74 31.03 49.85 87.49
s
12.84 13.26 14.50 16.59 20.75 33.24 54.06 95.70
s
Table 9. MAX 9000 Stand-Alone Verification Times for Different Test Clock Frequencies
Device
EPM9320
EPM9320A
EPM9400
EPM9480
EPM9560
EPM9560A
10 MHz 5 MHz
0.33
0.52
2 MHz
1.06
f_TCK
1 MHz 500 kHz 200 kHz 100 kHz
1.96
3.77
9.18
18.21
50 kHz
36.27
Units
s
0.36
0.57
1.20
0.39
0.63
1.34
0.42
0.69
1.48
2.24
2.53
2.81
4.33
10.60 21.05 41.95
s
4.90
12.02 23.89 47.63
s
5.47
13.44 26.73 53.31
s
22
Altera Corporation