EPM9560RC240-15 Datasheet, PDF (21/46 Pages) Altera Corporation – Programmable Logic Device Family

MAX 9000 Programmable Logic Device Family Data Sheet
By combining the pulse and shift times for each of the programming
stages, the program or verify time can be derived as a function of the TCK
frequency, the number of devices, and specific target device(s). Because
different ISP-capable devices have a different number of EEPROM cells,
both the total fixed and total variable times are unique for a single device.
Programming a Single MAX 9000 Device
The time required to program a single MAX 9000 device in-system can be
calculated from the following formula:
tPR _OG = tPP _ULSE + -^C----^y---^c-_f--_Tl---^e--_CP----_KT----^C-----^K--
where: t_PROG
t_PPULSE
Cycle_PTCK
f_TCK
= Programming time
= Sum of the fixed times to erase, program, and
verify the EEPROM cells
= Number of TCK cycles to program a device
= TCK frequency
The ISP times for a stand-alone verification of a single MAX 9000 device
can be calculated from the following formula:
tVER = tVPULSE + ^C-----^y---^c--_f-^l-_T-^e---_CV----_K-^T----^C----^K---
where: t_VER
= Verify time
t_VPULSE = Sum of the fixed times to verify the EEPROM cells
Cycle_VTCK = Number of TCK cycles to verify a device
Altera Corporation
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