ER3110DI Datasheet, PDF (20/23 Pages) Altera Corporation – Synchronous Buck Regulator

Example: V_PVIN = 12V, V_O = 5V, I_O = 1A, F_SW = 500kHz,
60
R₂ = 90.9kΩ, C_o = 22µF/5m?, L = 39µH, f_c = 50kHz, then
compensator resistance R₆:
45
R₆ = 22.75× 10³ ⋅ 50kHz ⋅ 5V ⋅ 22μF = 125.12kΩ
(EQ. 12)
30
It is acceptable to use 124kΩ as the closest standard value for
15
R₆.
C₆ = _{1--5--A--V---â‹}--^â‹----1-2--2-2--4--^μ-k---F_Ω-- = 0.88nF
0
(EQ. 13)
-15
C₇= max(5----m-----1^Ω--2---^â‹_{4----k--2-Ω}--2----^μ---F-,_π-----_â‹------5---0---0---k---H---1--z----_â‹-----1---2---4----k---_Ω--)= (0.88pF,5.1pF)
-30
100
1k
10k
100k
1M
(EQ. 14)
FREQUENCY (Hz)
It is also acceptable to use the closest standard values for C₆ and
180
C₇. There is approximately 3pF parasitic capacitance from V_COMP
to GND; Therefore, C₇ is optional. Use C₆ = 1500pF and C₇ =
150
OPEN.
C₃= _π-----_â‹------5---0---k----H----z1---_â‹------9---0---.--9---k---_Ω--- = 70pF
120
(EQ. 15)
90
Use C₃ = 68pF. Note that C₃ may increase the loop bandwidth
from previous estimated value. Figure 49 shows the simulated
voltage loop gain. It is shown that it has a 75kHz loop
bandwidth with a 61° phase margin and 6dB gain margin. It
may be more desirable to achieve an increased gain margin.
This can be accomplished by lowering R₆ by 20% to 30%. In
practice, ceramic capacitors have significant derating on
voltage and temperature, depending on the type. Please refer
to the ceramic capacitor datasheet for more details.
60
30
0
100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 49. SIMULATED LOOP GAIN
Enpirion Power Datasheet ER3110DI Wide PVIN 1A Synchronous Buck Regulator
10038
May 28, 2014
May 2014 Altera Corporation
Rev A