ER3110DI Datasheet, PDF(19/23 Page) Altera Corporation

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ER3110DI Datasheet, PDF (19/23 Pages) Altera Corporation – Synchronous Buck Regulator

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Page 19

VFB

VREF

VCOMP

FIGURE 48. TYPE II COMPENSATOR

Figure 48 shows the type II compensator and its transfer function is expressed as shown in Equation 8:

Av(S)=

v-Ë--C----O---M-----P-

vË FB

(---C---6-----+----C--G--7--M-)----â-â----(--R-R---3-2----+-----R----3---)

S---ââ-ââ--1-1---+--+----Ï---Ï-----c--S---c---Sz----p-----1----1-â â--â â--ââ-ââ-1--1---+--+----Ï----Ï----c-S-----c--z-S----p--2------2-â â--â â-

(EQ. 8)

where,

Ïcz1 = R----6--1--C---6- , Ïcz2 = R----2--1--C---3-, Ïcp1= R-C---6-6--C--+--6---CC---7-7-, Ïcp2= C-R---3-2--R--+--2---RR----33-

Compensator design goal:

High DC gain

Choose loop bandwidth fc less than 100kHz

Gain margin: >10dB

Phase margin: >40Â°

The compensator design procedure is as follows:

The loop gain at crossover frequency of fc has a unity gain. Therefore, the compensator resistance R6 is determined by

Equation 9.

R6 = -2--G-Ï---M-f-c---V-â---o---CV---o-F--B-R---t = 22.75Ã 103 â fcVoCo

(EQ. 9)

Where GM is the trans-conductance, gm, of the voltage error amplifier in each phase. Compensator capacitor C6 is then

given by Equation 10.

C6 = R----Ro----C6---o- = -VI--o-o--R-C---6-o-,C7= max(-R---Rc---C-6---o-,Ï----f--S---1W-----R----6-)

(EQ. 10)

Put one compensator pole at zero frequency to achieve high DC gain, and put another compensator pole at either ESR

zero frequency or half switching frequency, whichever is lower in Equation 10. An optional zero can boost the phase

margin. ÏCZ2 is a zero due to R2 and C3.

Put compensator zero 2 to 5 times fc

C3= Ï----f--c1---R----2-

(EQ. 11)

May 2014 Altera Corporation

10038

Enpirion Power Datasheet ER3110DI Wide PVIN 1A Synchronous Buck Regulator

May 28, 2014

Rev A

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