ER3110DI Datasheet, PDF (14/23 Pages) Altera Corporation – Synchronous Buck Regulator

Page 14
The buck regulator is equipped with an internal current sensing circuit and the peak current limit threshold is typically
set at 1.5A.
Power-On Reset
The ER3110DI automatically initializes upon receipt of the input power supply and continually monitors the EN pin
state. If EN is held below its logic rising threshold the IC is held in shutdown and consumes typically 2µA from the
V_PVIN supply. If EN exceeds its logic rising threshold, the regulator will enable the bias LDO and begin to monitor the
AVINO pin voltage. When the AVINO pin voltage clears its rising POR threshold, the controller will initialize the
switching regulator circuits. If AVINO never clears the rising POR threshold, the controller will not allow the
switching regulator to operate. If AVINO falls below its falling POR threshold while the switching regulator is
operating, the switching regulator will be shut down until AVINO returns.
Soft-Start
To avoid large in-rush current, V_OUT is slowly increased at startup to its final regulated value. Soft-start time is
determined by the SS pin connection. If SS is pulled to AVINO, an internal 2ms timer is selected for soft-start. For other
soft-start times, simply connect a capacitor from SS to GND. In this case, a 5.5µA current pulls up the SS voltage and
the FB pin will follow this ramp until it reaches the 600mV reference level. Soft-start time for this case is described by
Equation 1:
Time(ms) = C(nF)∗ 0.109
(EQ. 1)
Power-Good
POK is the open-drain output of a window comparator that continuously monitors the buck regulator output voltage
via the FB pin. POK is actively held low when EN is low and during the buck regulator soft-start period. After the soft-
start period completes, POK becomes high impedance provided the FB pin is within the range specified in the
“Electrical Specifications” on page 6. Should FB exit the specified window, POK will be pulled low until FB returns.
Over-temperature faults also force POK low until the fault condition is cleared by an attempt to soft-start. There is an
internal 5MΩ internal pull-up resistor.
PWM Control Scheme
The ER3110DI employs peak current-mode pulse-width modulation (PWM) control for fast transient response and
pulse-by-pulse current limiting, as shown in the “Functional Block Diagram” on page 13. The current loop consists of the
current sensing circuit, slope compensation ramp, PWM comparator, oscillator and latch. Current sense trans-resistance
is typically 500mV/A and slope compensation rate, Se, is typically 450mV/T where T is the switching cycle period. The
control reference for the current loop comes from the error amplifier’s output (V_COMP).
A PWM cycle begins when a clock pulse sets the PWM latch and the upper FET is turned on. Current begins to ramp up in
the upper FET and inductor. This current is sensed (V_CSA), converted to a voltage and summed with the slope compensation
signal. This combined signal is compared to V_COMP and when the signal is equal to V_COMP, the latch is reset. Upon latch reset
the upper FET is turned off and the lower FET turned on allowing current to ramp down in the inductor. The lower FET will
remain on until the clock initiates another PWM cycle. Figure 44 shows the typical operating waveforms during the PWM
operation. The dotted lines illustrate the sum of the current sense and slope compensation signal.
Output voltage is regulated as the error amplifier varies VCOMP and thus output inductor current. The error
amplifier is a trans-conductance type and its output (COMP) is terminated with a series RC network to GND. This
termination is internal (150k/54pF) if the COMP pin is tied to AVINO. Additionally, the trans-conductance for COMP
= AVINO is 50µA/V vs 230µA/V for external RC connection. Its non-inverting input is internally connected to a
600mV reference voltage and its inverting input is connected to the output voltage via the FB pin and its associated
divider network.
Enpirion Power Datasheet ER3110DI Wide PVIN 1A Synchronous Buck Regulator
10038
May 28, 2014
May 2014 Altera Corporation
Rev A