EV1340QI Datasheet, PDF (2/20 Pages) Enpirion, Inc. – 5A Synchronous Highly Integrated DC-DC DDR2/3/QDRTM Memory Termination and Low VIN Power SoC

Ordering Information
EV1340QI
Pin Assignments (Top View)
Part Number
EV1340QI
EVB-EV1340QI
Temp Rating
(°C)
Package
-40 to +85
54-pin QFN T&R
QFN Evaluation Board
Figure 3: Pinout Diagram (Top View).
All pins must be soldered to PCB
NOTE: There are specific keep-out areas underneath the
EV1340 to consider when laying out a PCB for this device.
Please see Figures 8, 10, and 11 for more layout details.
Pin Description
PIN
1-9, 18,
36, 37, 53,
54
10 -17
19, 20,
21-27
28-31
32
33, 39
34
35
38
40
41
42
NAME
NC
VOUT
SW
PGND
VDDQ
AGND2
AVIN1,
AVIN2
VDDB
BGND
ENABLE
AGND
POK
VFB
FUNCTION
NO CONNECT: These pins must be soldered to PCB but not electrically connected to each
other or to any external signal, voltage, or ground. These pins may be connected internally.
Failure to follow this guideline may result in device damage.
Regulated converter output. Decouple with output filter capacitor to PGND. Refer to layout
section for specific layout requirements
These pins are internally connected to the common switching node of the internal MOSFETs.
The anode of a Schottky diode needs to be connected to these pins. The cathode of the
diode needs to be connected to VDDQ.
Input and output power ground. Refer to layout section for specific layout requirements.
In DDR applications the input to this pin is the DDR core voltage. This is the input power
supply to the power train which will be divided by two to create an output voltage that tracks
with the input voltage applied to this pin. Decouple with input capacitor to PGND. Refer to
layout section for specific layout requirements
Ground for the gate driver supply. Connect to the GND plane with a via next to the pin.
Analog input voltage for the controller circuits. Each of these pins needs to be separately
connected to the 3.3V input supply. Decouple with a capacitor to AGND.
Internal regulated voltage used for the internal control circuitry. This pin is reserved for Altera
Enpirion testing, and should be left floating.
This pin is reserved for Altera Enpirion testing, and should be left floating.
This is the Device Enable pin. Floating this pin or a high level enables the device while a low
level disables the device.
This is the quiet ground for the controller. Connect to the GND plane with a via next to the pin.
POK is a logical AND of VDDQOK and the internally generated POK of the EV1340. POK is
an open drain logic output that requires an external pull-up resistor. This pin guarantees a
logic low even when the EV1340 is completely un-powered. This pin can sink a maximum
4mA. The pull-up resistor may be connected to a power supply other than AVIN or VDDQ but
the voltage should be <3.6Volts.
This is the feedback input pin which is always active. A resistor divider connects from the
output to AGND. The mid-point of the resistor divider is connected to VFB. (A feed-forward
capacitor and a resistor are required across the upper resistor.) The output voltage regulates
so as to make the VFB node voltage = 600mV.
06218
2
March 24, 2015
www.altera.com/enpirion
Rev C