EV1340QI Datasheet, PDF (12/20 Pages) Enpirion, Inc. – 5A Synchronous Highly Integrated DC-DC DDR2/3/QDRTM Memory Termination and Low VIN Power SoC

EV1340QI
Functional Description
Synchronous Buck Converter
The EV1340 is a synchronous, programmable
buck power supply with integrated power
MOSFET switches and integrated inductor.
The switching supply uses voltage mode
control and a low noise PWM topology. Two
power sources are required to operate this
device; a power supply for the controller (AVIN)
with a nominal input voltage range of 2.9-3.7V.
The second supply (VDDQ) is the supply that
is tracked - the recommended operating range
is 1.0 to 1.8V. With the right choice of input and
output dividers, the output voltage of the
EV1340 will produce an output voltage which
tracks to ½ VDDQ. The EV1340 can
continuously source or sink currents up to 5A.
The 1.5MHz nominal switching frequency
enables small-size input and output capacitors.
Enable Operation
The ENABLE pin provides a means to enable
normal operation or to shut down the device.
When the ENABLE pin is asserted (high) the
device will undergo a normal soft-start. A logic
low on this pin will power the device down.
Soft-Start and Soft-Shutdown
The EV1340 can operate with the controller
power supply (AVIN) ON, ENABLE High, and
VDDQ ramped up and down at a relatively
slow rate (~1V/ms). It is also expected that
VDDQ may be dynamically scaled within a
small voltage range. If, however, VDDQ should
ramp up at a high rate, or if the device is
enabled with a stable VDDQ, a capacitor
connected between VREF and AGND provides
the soft-start function to limit in-rush current.
The soft-start time constant is determined by
the input voltage divider and the soft-start
capacitor. See Figure 5.
the pre-bias value to the programmed output
voltage. Monotonic start-up is guaranteed for
pre-bias voltages in the range of >20% to
<85% of the programmed output voltage.
Outside of this range, the output voltage may
not rise monotonically. The Pre-Bias feature is
controlled by the EN_PB pin. For the pre-Bias
feature to function properly, VDDQ must be
stable, and the device must be turned on and
off using the ENABLE pin.
VDDQOK Operation
The VDDQOK pin can be used to indicate that
the VDDQ voltage is in regulation by tying it to
an upstream POK signal. The upstream device
is assumed to be driving the EV1340QI.
VDDQOK is internally pulled up to 2.5V
through a 94k resistor and is AND’ed with the
POK of the EV1340QI. The VDDQOK’s high
logic level voltage is clamped at a diode drop
above 2.5V. VDDQOK signal must be high in
order for the POK of the EV1340QI to be high.
POK Operation
The internal EV1340 POK is AND’ed with the
VDDQOK input. POK is meant to be used with
VDDQOK in a tracking application with VDDQ
ramping. The VDDQOK input is assumed to be
driven by the upstream VDDQ regulator’s POK
output. Normally the VDDQOK input indicates
that VDDQ has settled to the required level. If
VDDQ is dynamically switched, VDDQOK is
expected to mask the EV1340 POK during the
voltage transition. POK is de-asserted low 64
clock cycles (~43µs at 1.5MHz) after the falling
VOUT voltage crosses 45% (nominal) of
VDDQ. POK is also de-asserted if VOUT
exceeds 55% (nominal) of VDDQ. For proper
POK thresholds, the input voltage divider must
generate VREF nominally set to 0.4*VDDQ.
Pre-Bias Start-up
The EV1340 supports start up into a pre-
biased load. A proprietary circuit ensures the
output voltage ramps up monotonically from
Over-Current Protection
The current limit function is achieved by
sensing the current flowing in the hi-Side FET.
When the sensed current exceeds the current
limit, the PWM pulse is terminated for the rest
06218
12
March 24, 2015
www.altera.com/enpirion
Rev C