EV1340QI Datasheet, PDF (18/20 Pages) Enpirion, Inc. – 5A Synchronous Highly Integrated DC-DC DDR2/3/QDRTM Memory Termination and Low VIN Power SoC

EV1340QI
Design Considerations for Lead-Frame Based Modules
Exposed Metal on Bottom of Package
Package lead frames offer advantages in
thermal performance, in reduced electrical lead
resistance, and in overall foot print. They do,
however, require some special considerations.
In the assembly process, lead-frame
construction requires-for mechanical support-
that some of the lead-frame cantilevers be
exposed at the point where wire-bonds or
internal passives are attached. Because of this
lead frame requirement, several small pads are
exposed on the bottom of the package. Only
the large thermal pad and the perimeter pads
should be mechanically or electrically
connected to the PC board. The PCB top layer
under the EV1340 should be clear of any metal
except for the large thermal pad. The hatched
area in Figure 10 represents the area that
should be clear of all metal (traces, vias, or
planes) on the top layer of the PCB.
Figure 10: Lead-Frame Exposed Metal (Bottom View). The dimensioned hatched area highlights
exposed metal below the device which should not be soldered down. There should not be any metal
(traces, vias, or planes) on the top layer of the PCB below the hatched area.
06218
18
March 24, 2015
www.altera.com/enpirion
Rev C