EN2342QI Datasheet, PDF (16/23 Pages) Altera Corporation – 4A PowerSoC Voltage Mode Synchronous PWM Buck with Integrated Inductor

reached the device stops switching, the output will
be discharged and the cycle repeats itself
indefinitely. The equation below can be used to
estimate the maximum output capacitance allowed
based on current limit. Since the maximum output
capacitance in the calculation does not account for
temperature or part to part variations, it is always
good to add margin by using a value that is 80% of
the calculated output capacitance value.
C_{OUT_MAX} = I_TOTAL * dt / dv * 0.8
C_{OUT_MAX} = Maximum allowable output capacitance
I_TOTAL = Max output current of device minus the load
during startup
dv = Change in voltage (which is 0 to V_OUT)
dt = Soft-start time (ms) ≈ C_ss [nF] x 0.067
The output capacitance can also influence the
output ripple. Output ripple voltage is determined by
the aggregate output capacitor impedance.
Capacitor impedance, denoted as Z, is comprised
of capacitive reactance, effective series resistance,
ESR, and effective series inductance, ESL
reactance.
Placing output capacitors in parallel reduces the
impedance and will hence result in lower ripple
voltage.
1 11
1
= + + ... +
Z
ZZ
Z
Total
1
2
n
Recommended Output Capacitors
Description
47µF, 6.3V, X5R,
20%, 1206
MFG
Murata
P/N
GRM31CR60J476ME19L
47µF, 10V, X5R,
20%, 1206
Taiyo
Yuden
LMK316BJ476ML-T
22µF, 10V, X5R,
20%, 0805
Panasonic ECJ-2FB1A226M
22µF, 10V, X5R,
20%, 0805
Taiyo
Yuden
LMK212BJ226MG-T
Table 5: Recommended Output Capacitors
EN2342QI
09520
February 21, 2014
www.altera.com/enpirion, Page 16
Rev A