EN2342QI Datasheet, PDF (13/23 Pages) Altera Corporation – 4A PowerSoC Voltage Mode Synchronous PWM Buck with Integrated Inductor

Rfs vs. SW Frequency
1.80
1.70
1.60
1.50
1.40
1.30
1.20
1.10
1.00
0.90
0.80
0.70
CONDITIONS
V_IN = 6V to 12V
V_OUT = 0.8V to 5.0V
0.60
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
R_FS RESISTOR VALUE (kΩ)
Figure 7. Typical R_FS vs. Switching Frequency
PVIN
4.5V
to
14V
VOUT
5.0V
3.3V
2.5V
1.8V
1.5V
1.2V
<1.0V
R_FS
30k
15k
10k
4.87k
3.01k
3.01k
3.01k
Typical fsw
1.48 MHz
1.38 MHz
1.3 MHz
1.15 MHz
1.0 MHz
1.0 MHz
1.0 MHz
Table 1: Recommended R_FS Values
Spread Spectrum Mode
The external clock frequency may be swept
between 0.9MHz and 1.8MHz at repetition rates of
up to 10 kHz in order to reduce EMI frequency
components.
Soft-Start Operation
Soft start is a means to ramp the output voltage
gradually upon start-up. The output voltage rise
time is controlled by the choice of soft-start
capacitor, which is placed between the SS pin (pin
56) and the AGND pin (pin 52). During start-up of
the converter, the reference voltage to the error
amplifier is linearly increased to its final level by an
internal current source of approximately 10µA. The
soft-start time is measured from when V_IN > V_UVLOR
and ENABLE pin voltage crosses its logic high
threshold to when V_OUT reaches its programmed
value. The total soft-start time can be calculated by:
Soft Start Time (ms): T_SS ≈ C_ss [nF] x 0.067
Typical soft-start time is approximately 3.2ms with
SS capacitor value of 47nF.
EN2342QI
POK Operation
The POK signal is an open drain signal (requires a
pull up resistor to AVIN or similar voltage) from the
converter indicating the output voltage is within the
specified range. Typically, a 100kΩ or lower
resistance is used as the pull-up resistor. The POK
signal will be logic high (AVIN) when the output
voltage is above 90% of the programmed voltage
level. If the output voltage is below this point, the
POK signal will be a logic low. The POK signal can
be used to sequence down-stream converters by
tying to their enable pins.
Over-Current Protection (OCP)
The current limit function is achieved by sensing
the current flowing through a sense PFET. When
the sensed current exceeds the current limit for
more than 32 cycles, both power FETs are turned
off for the rest of the switching cycle. If the over-
current condition is removed, the over-current
protection circuit will re-enable PWM operation. In
the event the OCP circuit trips consistently in
normal operation, the device enters a hiccup mode.
While in hiccup mode, the device is disabled for a
short while and restarted with a normal soft-start.
The hiccup time is approximately 32ms. This cycle
can continue indefinitely as long as the over current
condition persists. The OCP trip point depends on
PVIN, VOUT, RCLX, RFS and will vary from part to
part. The current limit is meant to protect the device
from damage and not recommended as an
accurate current limit setting. Generally, the higher
the RCLX value, the higher the current limit
threshold for a given input and output voltage
condition. Since current limit depends on various
parameters, follow Table 2 for recommended
values to cover most applications.
Note: If the RCLX pin is left open, the output
current will be unlimited and the device will not
have current limit protection.
PVIN
4.5V
to
14V
V_OUT
5.0V
3.3V
2.5V
1.8V
1.5V
1.2V
≤1.0V
R_CLX
68.1k
61.9k
56.2k
54.9k
53.6k
46.4k
38.3k
R_FS
30k
22k
10k
4.87k
3.01k
3.01k
3.01k
Table 2: Recommended R_CLX Values
www.altera.com/enpirion, Page 13
09520
February 21, 2014
Rev A