EN2342QI Datasheet, PDF (12/23 Pages) Altera Corporation – 4A PowerSoC Voltage Mode Synchronous PWM Buck with Integrated Inductor

Modes of Operation
The EN2342QI is designed to be powered by either
a single input supply (PVIN) or two separate
supplies: one for PVIN and the other for AVIN. The
EN2342QI is not “hot pluggable.” Refer to the PVIN
Slew Rate specification on page 4.
Single Input Supply Application (PVIN Only):
22nF
0.22 F
V_IN
22 F
1206
RVB
4.75k
F
ON
OFF
F
47nF
PG BTMP VDDB BGND
PVIN
VOUT
EN2342QI
ENABLE
AVINO
AVIN
VFB
SS
PGND
FQADJ AGND
PGND
RCLX
V_OUT
COUT
RA
CA
RCA
RB
RFS
RCLX
Figure 5: Single Input Supply Schematic
In single input supply mode, the EN2342QI only
requires one input voltage rail (typically 12V). The
EN2342QI has an internal linear regulator that
converts PVIN to 3.3V. The output of the linear
regulator is provided on the AVINO pin once the
device is enabled. AVINO should be connected to
AVIN. Also, in this single supply application, place a
resistor (R_VB) between VDDB and AVIN, as shown
in Figure 5. Altera recommends R_VB=4.75kΩ.
Dual Input Supply Application (PVIN and AVIN):
22nF
0.22 F
V_IN
22 F
1206
V_AVIN
ON
OFF
F
47nF
PG BTMP VDDB BGND
PVIN
VOUT
EN2342QI
ENABLE
AVINO
AVIN
VFB
SS
PGND
FQADJ AGND
PGND
RCLX
V_OUT
COUT
RA
CA
RCA
RB
RFS
RCLX
Figure 6: Dual Input Supply Schematic
In dual input supply mode, two input voltage rails
are required (typically 12V for PVIN and 3.3V for
AVIN). Refer to Figure 6 for the recommended
schematic for a dual input supply application.
Since AVINO is not used, it can be left open.
EN2342QI
Enable Operation
The ENABLE pin provides a means to enable
normal operation or to shut down the device. A
logic high will enable the converter into normal
operation. When the ENABLE pin is asserted (high)
the device will undergo a normal soft-start. A logic
low will disable the converter. A logic low will power
down the device in a controlled manner and the
device is subsequently shut down. The ENABLE
signal has to be low for at least the ENABLE
Lockout Time (8ms) in order for the device to be re-
enabled. To ensure accurate startup sequencing
the ENABLE/DISABLE signal should be faster than
1V/100µs. A slower ENABLE/DISABLE signal may
result in a delayed startup and shutdown response.
Do not leave ENABLE floating.
Pre-Bias Precaution
The EN2342QI is not designed to be turned on into
a pre-biased output voltage. Be sure the output
capacitors are not charged or the output of the
EN2342QI is not pre-biased when the EN2342QI is
first enabled.
Frequency Synchronization
The switching frequency of the EN2342QI can be
phase-locked to an external clock source to move
unwanted beat frequencies out of band. The
internal switching clock of the EN2342QI can be
phase locked to a clock signal applied to the S_IN
pin. An activity detector recognizes the presence of
an external clock signal and automatically phase-
locks the internal oscillator to this external clock.
Phase-lock will occur as long as the input clock
frequency is in the range of 0.9MHz to 1.8MHz. The
external clock frequency must be within ±10% of
the nominal switching frequency set by the R_FS
resistor. It is recommended to use a synchronized
clock frequency close to the typical frequency
recommendations in Table 1. A 3.01kΩ resistor
from FQADJ to ground is recommended for clock
frequencies within ±10% of 1MHz. When no clock
is present, the device reverts to the free running
frequency of the internal oscillator set by the R_FS
resistor.
The efficiency performance of the EN2342QI for
various PVIN/VOUT combinations can be optimized
by adjusting the switching frequency. Table 1
shows recommended R_FS values for various
PVIN/VOUT combinations in order to optimize
performance of the EN2342QI.
www.altera.com/enpirion, Page 12
09520
February 21, 2014
Rev A