MT48LC4M32B2TG-6A Datasheet, PDF (37/79 Pages) Alliance Semiconductor Corporation – MT48LC4M32B2 – 1 Meg x 32 x 4 Banks

128Mb: x32 SDRAM
Mode Register
Mode Register
The mode register defines the specific mode of operation, including burst length (BL),
burst type, CAS latency (CL), operating mode, and write burst mode. The mode register
is programmed via the LOAD MODE REGISTER command and retains the stored infor-
mation until it is programmed again or the device loses power.
Mode register bits M[2:0] specify the BL; M3 specifies the type of burst; M[6:4] specify
the CL; M7 and M8 specify the operating mode; M9 specifies the write burst mode; and
M10–Mn should be set to zero to ensure compatibility with future revisions. Mn + 1 and
Mn + 2 should be set to zero to select the mode register.
The mode registers must be loaded when all banks are idle, and the controller must wait
t_{MRD before initiating the subsequent operation. Violating either of these requirements}
will result in unspecified operation.
PDF: 09005aef80872800
128mb_x32_sdram.pdf - Rev. V 03/16 EN
37
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