MT48LC4M32B2TG-6A Datasheet, PDF (29/79 Pages) Alliance Semiconductor Corporation – MT48LC4M32B2 – 1 Meg x 32 x 4 Banks

REFRESH
AUTO REFRESH
SELF REFRESH
128Mb: x32 SDRAM
Commands
AUTO REFRESH is used during normal operation of the SDRAM and is analogous to
CAS#-BEFORE-RAS# (CBR) refresh in conventional DRAMs. This command is nonper-
sistent, so it must be issued each time a refresh is required. All active banks must be pre-
charged prior to issuing an AUTO REFRESH command. The AUTO REFRESH command
should not be issued until the minimum ^tRP has been met after the PRECHARGE com-
mand, as shown in Bank/Row Activation (page 42).
The addressing is generated by the internal refresh controller. This makes the address
bits a “Don’t Care” during an AUTO REFRESH command. Regardless of device width,
the 128Mb SDRAM requires 4096 AUTO REFRESH cycles every 64ms (commercial and
industrial) or 16ms (automotive). Providing a distributed AUTO REFRESH command
every 15.625μs (commercial and industrial) or 3.906μs (automotive) will meet the re-
fresh requirement and ensure that each row is refreshed. Alternatively, 4096 AUTO RE-
FRESH commands can be issued in a burst at the minimum cycle rate (^tRFC), once ev-
ery 64ms (commercial and industrial) or 16ms (automotive).
The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest
of the system is powered-down. When in the self refresh mode, the SDRAM retains data
without external clocking.
The SELF REFRESH command is initiated like an AUTO REFRESH command except
CKE is disabled (LOW). After the SELF REFRESH command is registered, all the inputs
to the SDRAM become a “Don’t Care” with the exception of CKE, which must remain
LOW.
After self refresh mode is engaged, the SDRAM provides its own internal clocking, caus-
ing it to perform its own AUTO REFRESH cycles. The SDRAM must remain in self re-
fresh mode for a minimum period equal to ^tRAS and may remain in self refresh mode
for an indefinite period beyond that.
The procedure for exiting self refresh requires a sequence of commands. First, CLK
must be stable (stable clock is defined as a signal cycling within timing constraints
specified for the clock pin) prior to CKE going back HIGH. After CKE is HIGH, the
SDRAM must have NOP commands issued (a minimum of two clocks) for ^tXSR because
time is required for the completion of any internal refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH commands must be issued at the
specified intervals, as both SELF REFRESH and AUTO REFRESH utilize the row refresh
counter.
Self refresh is not supported on automotive temperature devices.
PDF: 09005aef80872800
128mb_x32_sdram.pdf - Rev. V 03/16 EN
29
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