MT48LC4M32B2TG-6A Datasheet, PDF (1/79 Pages) Alliance Semiconductor Corporation – MT48LC4M32B2 – 1 Meg x 32 x 4 Banks

SDR SDRAM
MT48LC4M32B2 – 1 Meg x 32 x 4 Banks
128Mb: x32 SDRAM
Features
Features
• PC100-compliant
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto precharge
and auto refresh modes
• Self refresh mode (not available on AT devices)
• Auto refresh
– 64ms, 4096-cycle refresh (commercial and
industrial)
– 16ms, 4096-cycle refresh (automotive)
• LVTTL-compatible inputs and outputs
• Single 3.3V ±0.3V power supply
• Supports CAS latency (CL) of 1, 2, and 3
Options
• Configuration
– 4 Meg x 32 (1 Meg x 32 x 4 banks)
• Package – OCPL¹
– 86-pin TSOP II (400 mil)
– 86-pin TSOP II (400 mil) Pb-free
– 90-ball VFBGA (8mm x 13mm)
– 90-ball VFBGA (8mm x 13mm) Pb-
free
• Timing (cycle time)
– 6ns (167 MHz)
– 6ns (167 MHz)
– 7ns (143 MHz)
• Revision
• Operating temperature range
– Commercial (0°C to +70°C)
– Industrial (–40°C to +85°C)
– Automotive (–40°C to +105°C)
Marking
4M32B2
TG
P
F5
B5
-6A²
-6³
-7³
:G/:L
None
IT
AT⁴
Notes:
1. Off-center parting line.
2. Available only on Revision L.
3. Available only on Revision G.
4. Contact Micron for availability.
Table 1: Key Timing Parameters
CL = CAS (READ) latency
Clock
Speed Grade
Frequency (MHz)
-6A
167
-6
167
-7
143
Target ^tRCD-^tRP-CL
3-3-3
3-3-3
3-3-3
t_{RCD (ns)}
18
18
20
t_{RP (ns)}
18
18
20
CL (ns)
18
18
21
PDF: 09005aef80872800
128mb_x32_sdram.pdf - Rev. V 03/16 EN
1
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Products and specifications discussed herein are subject to change by Micron without notice.