AKD4584 Datasheet, PDF (9/41 Pages) Asahi Kasei Microsystems – Evaluation board Rev.A for AK4584

ASAHI KASEI
[AKD4584]
(1-4) All interfacing signal (MCLK, BICK, LRCK) are fed from the external circuit
Using PORT6 (ROM). Nothing should be connected to J7 (RX), PORT1 (DIR) and PORT5 (DIR). Remove the
X’tal (X1). JP6 (EXT) should be short. In normal speed, double speed mode and quad speed mode, JP1 (MCKO),
JP4 (MCLK), JP5 (BCFS) and JP7 (LRFS) should be open.
JP3
JP6
XTI
EXT
JP10
MCLK
JP11
BICK
JP14
LRCK
JP15
SDTI
DIR EXT DIR EXT DIR ADC
• SW2 (MODE) setting (See Table 1)
(1) When XTALE is “H”, MCLK can output from MCKO1/2 pins though AK4584 is powered down.
(2) When DMCK is “H”, MCKO1 output is disabled.
H 1 2 3 4 5 6 7 8 9 10
L
<KM065800>
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